Lines Matching defs:MI

223 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,  in getMachineOpValue()
234 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, in getLdStUImm12OpValue()
255 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, in getAdrLabelOpValue()
281 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, in getAddSubImmOpValue()
318 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getCondBranchTargetOpValue()
339 AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx, in getPAuthPCRelOpValue()
362 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, in getLoadLiteralOpValue()
382 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, in getMemExtendOpValue()
391 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, in getMoveWideImmOpValue()
411 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getTestBranchTargetOpValue()
432 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, in getBranchTargetOpValue()
460 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, in getVecShifterOpValue()
485 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getFixedPointScaleOpValue()
493 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftR64OpValue()
502 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftR32OpValue()
511 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftR16OpValue()
520 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftR8OpValue()
529 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftL64OpValue()
538 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftL32OpValue()
547 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftL16OpValue()
556 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, in getVecShiftL8OpValue()
566 AArch64MCCodeEmitter::EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx, in EncodeRegAsMultipleOf()
576 AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx, in EncodePNR_p8to15()
584 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in EncodeZPR2StridedRegisterClass()
594 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in EncodeZPR4StridedRegisterClass()
604 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in EncodeMatrixTileListRegisterClass()
613 AArch64MCCodeEmitter::encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx, in encodeMatrixIndexGPR32()
621 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx, in getImm8OptLsl()
639 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx, in getSVEIncDecImm()
651 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, in getMoveVecShifterOpValue()
661 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue, in fixMOVZ()
693 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, in encodeInstruction()
722 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI, in fixMulHigh()
732 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, in fixLoadStoreExclusive()
742 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const { in fixOneOperandFPComparison() argument