Lines Matching full:ld1
434 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
435 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
436 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
437 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
438 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
439 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
440 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
441 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
458 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
459 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
460 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
461 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
462 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
463 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
464 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
465 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
466 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
467 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
468 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
469 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
470 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
471 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
472 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
473 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
474 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
475 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
476 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
477 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
478 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
479 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
480 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
481 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
482 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
483 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
484 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
485 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
486 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
487 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
488 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
489 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
490 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
491 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
492 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
493 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
494 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
495 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
496 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
497 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
498 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
499 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
500 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
501 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
502 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
503 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
504 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
505 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
506 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
507 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
508 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
509 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
510 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
511 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
512 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
513 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
514 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
515 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
516 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
517 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
518 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
519 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
520 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
521 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },