Lines Matching +full:fine +full:- +full:tune
1 //===- AArch64RegisterBankInfo.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
77 "GPRs should hold up to 128-bit");
86 "FPRs should hold up to 512-bit via QQQQ sequence");
91 "CCR should hold up to 32-bit");
142 // Check the value mapping for 3-operands instructions where all the operands
162 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
163 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
192 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
193 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
300 const MachineFunction &MF = *MI.getParent()->getParent();
307 // 32 and 64-bit or can be mapped on either FPR or
313 // If the instruction has any implicit-defs or uses,
334 // If the instruction has any implicit-defs or uses,
374 // If the instruction has any implicit-defs or uses,
384 // Addresses are GPR 64-bit.
391 // Addresses are GPR 64-bit.
436 const MachineFunction &MF = *MI.getParent()->getParent();
529 // No. Check if we have a copy-like instruction. If we do, then we could
613 const Value *LdVal = MemOp->getMMO().getValue();
619 EltTy = GV->getValueType();
623 if (StructEltTy->getNumElements() == 0)
625 EltTy = StructEltTy->getTypeAtIndex(0U);
629 EltTy = EltTy->getArrayElementType();
633 for (const auto *LdUser : LdVal->users()) {
635 EltTy = LdUser->getType();
638 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
639 EltTy = LdUser->getOperand(0)->getType();
644 return EltTy && EltTy->isFPOrFPVectorTy();
651 // Try the default logic for non-generic instructions that are either copies
661 const MachineFunction &MF = *MI.getParent()->getParent();
724 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
767 // As a top-level guess, vectors including both scalable and non-scalable
769 // For floating-point instructions, scalars go in FPRs.
780 // Some of the floating-point instructions have mixed GPR and FPR operands:
781 // fine-tune the computed mapping.
788 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
809 // Integer to FP conversions don't necessarily happen between GPR -> FPR
878 // Int->FP conversion operations are also captured in
985 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
1053 unsigned DefOpc = DefMI->getOpcode();
1056 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1135 if (!Mapping->isValid())