Lines Matching defs:TRI
47 const TargetRegisterInfo &TRI) {
74 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
81 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
83 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
88 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
214 assert(verify(TRI) && "Invalid register bank information");
302 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
309 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
330 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
370 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
505 const TargetRegisterInfo &TRI, const unsigned Depth) const {
511 if (onlyUsesFP(UseMI, MRI, TRI, Depth + 1))
513 return isPHIWithFPContraints(UseMI, MRI, TRI, Depth + 1);
519 const TargetRegisterInfo &TRI,
536 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
551 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
557 const TargetRegisterInfo &TRI,
569 return hasFPConstraints(MI, MRI, TRI, Depth);
574 const TargetRegisterInfo &TRI,
607 return hasFPConstraints(MI, MRI, TRI, Depth);
664 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
712 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
713 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
721 TypeSize Size = getSizeInBits(DstReg, MRI, TRI);
792 (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
793 onlyDefinesFP(*ScalarDef, MRI, TRI)))
812 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank)
881 if (isPHIWithFPContraints(UseMI, MRI, TRI))
884 return onlyUsesFP(UseMI, MRI, TRI) ||
885 onlyDefinesFP(UseMI, MRI, TRI);
897 if (onlyDefinesFP(*DefMI, MRI, TRI))
908 if (onlyDefinesFP(*DefMI, MRI, TRI))
948 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))
967 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank ||
968 onlyDefinesFP(*DefMI, MRI, TRI))
990 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
1011 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
1062 getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank) {
1101 if (onlyDefinesFP(MI, MRI, TRI))
1110 if (onlyUsesFP(MI, MRI, TRI))