Lines Matching defs:Dst
74 Register Dst; ///< Destination register.
76 ShuffleVectorPseudo(unsigned Opc, Register Dst,
78 : Opc(Opc), Dst(Dst), SrcOps(SrcOps){};
161 Register Dst = MI.getOperand(0).getReg();
163 LLT Ty = MRI.getType(Dst);
183 MatchInfo = ShuffleVectorPseudo(Opcode, Dst, {Src});
198 Register Dst = MI.getOperand(0).getReg();
199 unsigned NumElts = MRI.getType(Dst).getNumElements();
205 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
219 Register Dst = MI.getOperand(0).getReg();
220 unsigned NumElts = MRI.getType(Dst).getNumElements();
226 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
235 Register Dst = MI.getOperand(0).getReg();
236 unsigned NumElts = MRI.getType(Dst).getNumElements();
242 MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
352 Register Dst = MI.getOperand(0).getReg();
353 LLT DstTy = MRI.getType(Dst);
367 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V1, Imm});
375 MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V2, Imm});
384 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps);
394 MIRBuilder.buildCopy(MatchInfo.Dst, MatchInfo.SrcOps[0]);
399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst},
469 Register Dst = MI.getOperand(0).getReg();
470 int NumElts = MRI.getType(Dst).getNumElements();
496 Register Dst = MI.getOperand(0).getReg();
497 auto ScalarTy = MRI.getType(Dst).getElementType();
504 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
924 assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
979 Register Dst = MI.getOperand(0).getReg();
980 LLT DstTy = MRI.getType(Dst);
1001 Register Dst = CmpMI.getReg(0);
1006 LLT DstTy = MRI.getType(Dst);
1047 MRI.replaceRegWith(Dst, CmpRes);