Lines Matching defs:Is32Bit

1187   const bool Is32Bit = Size == 32;
1189     unsigned Opc = Is32Bit ? AArch64::FCSELSrrr : AArch64::FCSELDrrr;
1196   unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr;
1198   auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI,
1213       Opc = Is32Bit ? AArch64::CSNEGWr : AArch64::CSNEGXr;
1230       Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
1249       Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
1265   auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI,
1274     Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
1281         Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
1289         Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
1300         Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
1309         Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
1321         Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
1328         Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
4275   bool Is32Bit = Size == 32;
4279     return emitInstr(AddrModeAndSizeToOpcode[0][Is32Bit], {Dst}, {LHS},
4284     return emitInstr(AddrModeAndSizeToOpcode[3][Is32Bit], {Dst}, {LHS},
4289     return emitInstr(AddrModeAndSizeToOpcode[4][Is32Bit], {Dst}, {LHS},
4294     return emitInstr(AddrModeAndSizeToOpcode[1][Is32Bit], {Dst}, {LHS},
4296   return emitInstr(AddrModeAndSizeToOpcode[2][Is32Bit], {Dst}, {LHS, RHS},
4345   bool Is32Bit = (MRI->getType(LHS.getReg()).getSizeInBits() == 32);
4347   return emitInstr(OpcTable[Is32Bit], {Dst}, {LHS, RHS}, MIRBuilder);
4356   bool Is32Bit = (MRI->getType(LHS.getReg()).getSizeInBits() == 32);
4358   return emitInstr(OpcTable[Is32Bit], {Dst}, {LHS, RHS}, MIRBuilder);
4365   bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
4366   auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;
4377   bool Is32Bit = (RegSize == 32);
4387       auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS});
4395     return emitInstr(OpcTable[1][Is32Bit], {Ty}, {LHS}, MIRBuilder, Fns);
4396   return emitInstr(OpcTable[2][Is32Bit], {Ty}, {LHS, RHS}, MIRBuilder);