Lines Matching defs:DstRC

149                                    const TargetRegisterClass *DstRC,
1016   const TargetRegisterClass *DstRC;
1017   std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
1019   if (!DstRC) {
1034     const TypeSize DstSize = TRI.getRegSizeInBits(*DstRC);
1042       getSubRegForClass(DstRC, TRI, SubReg);
1046       copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg);
1053       copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg);
1079   if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
3161       const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
3162       if (!DstRC)
3170           !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
3175       if (DstRC == SrcRC) {
3181       } else if (DstRC == &AArch64::GPR32RegClass &&
3474     const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
3475     RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
3732     unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
3734   auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {});
3739             .buildInstr(TargetOpcode::INSERT_SUBREG, {DstRC}, {Undef, Scalar})
3824   auto *DstRC = &AArch64::GPR64RegClass;
3825   Register SubToRegDef = MRI.createVirtualRegister(DstRC);
3832   Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);
3895   const TargetRegisterClass *DstRC =
3897   if (!DstRC) {
3914     DstReg = MRI.createVirtualRegister(DstRC);
3919     RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
3939   RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
4517   const TargetRegisterClass *DstRC =
4521       emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder);
4523       emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder);
4535     Dst = MRI.createVirtualRegister(DstRC);
5147   const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;
5152     DstReg = MRI.createVirtualRegister(DstRC);
5158     auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder);
5740   const TargetRegisterClass *DstRC =
5742   if (!DstRC)
5752   return RBI.constrainGenericRegister(Dst, *DstRC, MRI);
5773   const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;
5775       emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC,