Lines Matching defs:DstRB

321                                      const RegisterBank &DstRB, LLT ScalarTy,
2736       const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2737       assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!");
2754           DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB);
3151     const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
3154     if (DstRB.getID() != SrcRB.getID()) {
3160     if (DstRB.getID() == AArch64::GPRRegBankID) {
3161       const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
3192     } else if (DstRB.getID() == AArch64::FPRRegBankID) {
3202             DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB);
3473     const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
3474     const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
3884     std::optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy,
3896       getRegClassForTypeOnBank(ScalarTy, DstRB, true);
3972   const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
3973   MachineInstr *Extract = emitExtractVectorElt(DstReg, DstRB, NarrowTy, SrcReg,
3997   const RegisterBank &DstRB =
4002         emitExtractVectorElt(Dst, DstRB, NarrowTy, SrcReg, OpIdx, MIB);
5729   const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI);
5730   if (EltRB != DstRB)
5741       getRegClassForTypeOnBank(MRI.getType(Dst), DstRB);
7875   const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg);
7876   assert(DstRB && "Expected PHI dst to have regbank assigned");
7885     if (RB != DstRB) {
7898       MRI.setRegBank(Copy.getReg(0), *DstRB);