Lines Matching +full:sb +full:- +full:rmi
1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
238 /// @name Auto-generated Match Functions
309 // Alias .hword/.word/.[dx]word to the target-independent
341 /// AArch64Operand - Instances of this class represent a parsed AArch64 machine
591 /// getStartLoc - Get the location of the first token of this operand.
593 /// getEndLoc - Get the location of the last token of this operand.
789 int64_t Val = MCE->getValue();
821 Val = MCE->getValue();
826 int64_t Shift = Bits - 1;
827 MinVal = (int64_t(1) << Shift) * -Scale;
828 MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
831 MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
846 int64_t Val = MCE->getValue();
858 int64_t Val = MCE->getValue();
887 // Note that we don't range-check the addend. It's adjusted modulo page
908 int64_t Val = MCE->getValue();
919 int64_t Val = MCE->getValue();
933 int64_t Val = MCE->getValue();
935 uint64_t Upper = UINT64_C(-1) << (sizeof(T) * 4) << (sizeof(T) * 4);
936 // Allow all-0 or all-1 in top bits to permit bitwise NOT.
954 return std::make_pair(CE->getValue(), Width);
958 int64_t Val = CE->getValue();
1006 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff;
1019 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff;
1024 // Signed value in the range -128 to +127. For element widths of
1026 // range -32768 to +32512.
1027 // For element-width of 8 bits a range of -128 to 255 is accepted,
1037 if (!(IsByte && ShiftedImm->second) &&
1038 AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
1039 << ShiftedImm->second))
1055 if (!(IsByte && ShiftedImm->second) &&
1056 AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
1057 << ShiftedImm->second))
1077 return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue());
1087 int64_t Val = MCE->getValue();
1091 return (Val >= -((1<<(N-1)) << 2) && Val <= (((1<<(N-1))-1) << 2));
1148 uint64_t Value = CE->getValue();
1163 uint64_t Value = CE->getValue();
1170 AArch64_AM::getFP64Imm(getFPImm().bitcastToAPInt()) != -1;
1184 return SysReg.MRSReg != -1U;
1189 return SysReg.MSRReg != -1U;
1206 return SVCR.PStateField != -1U;
1344 // a shift-amount that does not match what is expected, but for which
1396 uint64_t Value = CE->getValue();
1451 if (((VectorList.RegNum - AArch64::Z0) % NumRegs) != 0)
1511 RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero);
1548 // Make sure the extend expects a 32-bit source register.
1683 int64_t Val = CE->getValue();
1684 int64_t Min = - (4096 * (1LL << (21 - 1)));
1685 int64_t Max = 4096 * ((1LL << (21 - 1)) - 1);
1699 int64_t Val = CE->getValue();
1700 int64_t Min = - (1LL << (21 - 1));
1701 int64_t Max = ((1LL << (21 - 1)) - 1);
1728 int64_t Val = MCE->getValue();
1731 return (Val <= 0) && (Val > -(1 << 18));
1739 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1760 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1761 RI->getEncodingValue(getReg()));
1772 uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
1773 RI->getEncodingValue(getReg()));
1790 Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1798 Reg = Reg - AArch64::PN0 + AArch64::P0;
1805 MCOperand::createReg((getReg() - AArch64::PN0) + AArch64::P0));
1812 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
1863 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
1878 AArch64::Z0_Z8 + getVectorListStart() - AArch64::Z0));
1883 AArch64::Z16_Z24 + getVectorListStart() - AArch64::Z16));
1891 AArch64::Z0_Z4_Z8_Z12 + getVectorListStart() - AArch64::Z0));
1896 AArch64::Z16_Z20_Z24_Z28 + getVectorListStart() - AArch64::Z16));
1926 // to be only the page-offset portion. Otherwise, just add the expr
1927 // as-is.
1935 Inst.addOperand(MCOperand::createImm(ShiftedVal->first));
1936 Inst.addOperand(MCOperand::createImm(ShiftedVal->second));
1950 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first));
1951 Inst.addOperand(MCOperand::createImm(ShiftedVal->second));
1967 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 12));
1983 Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
1989 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
1996 Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
2009 std::make_unsigned_t<T> Val = MCE->getValue();
2018 std::make_unsigned_t<T> Val = ~MCE->getValue();
2026 uint64_t encoding = AArch64_AM::encodeAdvSIMDModImmType10(MCE->getValue());
2041 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
2045 // PC-relative operands don't encode the low bits, so shift them off
2054 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
2068 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
2082 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
2171 uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID)
2172 .getRegister(RI->getEncodingValue(getReg()));
2203 // For 8-bit load/store instructions with a register offset, both the
2221 uint64_t Value = CE->getValue();
2233 uint64_t Value = CE->getValue();
2240 Inst.addOperand(MCOperand::createImm(MCE->getValue() / 90));
2246 Inst.addOperand(MCOperand::createImm((MCE->getValue() - 90) / 180));
2254 Op->Tok.Data = Str.data();
2255 Op->Tok.Length = Str.size();
2256 Op->Tok.IsSuffix = IsSuffix;
2257 Op->StartLoc = S;
2258 Op->EndLoc = S;
2269 Op->Reg.RegNum = RegNum;
2270 Op->Reg.Kind = Kind;
2271 Op->Reg.ElementWidth = 0;
2272 Op->Reg.EqualityTy = EqTy;
2273 Op->Reg.ShiftExtend.Type = ExtTy;
2274 Op->Reg.ShiftExtend.Amount = ShiftAmount;
2275 Op->Reg.ShiftExtend.HasExplicitAmount = HasExplicitAmount;
2276 Op->StartLoc = S;
2277 Op->EndLoc = E;
2293 Op->Reg.ElementWidth = ElementWidth;
2302 Op->VectorList.RegNum = RegNum;
2303 Op->VectorList.Count = Count;
2304 Op->VectorList.Stride = Stride;
2305 Op->VectorList.NumElements = NumElements;
2306 Op->VectorList.ElementWidth = ElementWidth;
2307 Op->VectorList.RegisterKind = RegisterKind;
2308 Op->StartLoc = S;
2309 Op->EndLoc = E;
2316 Op->VectorIndex.Val = Idx;
2317 Op->StartLoc = S;
2318 Op->EndLoc = E;
2325 Op->MatrixTileList.RegMask = RegMask;
2326 Op->StartLoc = S;
2327 Op->EndLoc = E;
2364 Op->Imm.Val = Val;
2365 Op->StartLoc = S;
2366 Op->EndLoc = E;
2375 Op->ShiftedImm .Val = Val;
2376 Op->ShiftedImm.ShiftAmount = ShiftAmount;
2377 Op->StartLoc = S;
2378 Op->EndLoc = E;
2387 Op->ImmRange.First = First;
2388 Op->ImmRange.Last = Last;
2389 Op->EndLoc = E;
2396 Op->CondCode.Code = Code;
2397 Op->StartLoc = S;
2398 Op->EndLoc = E;
2405 Op->FPImm.Val = Val.bitcastToAPInt().getSExtValue();
2406 Op->FPImm.IsExact = IsExact;
2407 Op->StartLoc = S;
2408 Op->EndLoc = S;
2418 Op->Barrier.Val = Val;
2419 Op->Barrier.Data = Str.data();
2420 Op->Barrier.Length = Str.size();
2421 Op->Barrier.HasnXSModifier = HasnXSModifier;
2422 Op->StartLoc = S;
2423 Op->EndLoc = S;
2433 Op->SysReg.Data = Str.data();
2434 Op->SysReg.Length = Str.size();
2435 Op->SysReg.MRSReg = MRSReg;
2436 Op->SysReg.MSRReg = MSRReg;
2437 Op->SysReg.PStateField = PStateField;
2438 Op->StartLoc = S;
2439 Op->EndLoc = S;
2446 Op->SysCRImm.Val = Val;
2447 Op->StartLoc = S;
2448 Op->EndLoc = E;
2457 Op->Prefetch.Val = Val;
2458 Op->Barrier.Data = Str.data();
2459 Op->Barrier.Length = Str.size();
2460 Op->StartLoc = S;
2461 Op->EndLoc = S;
2470 Op->PSBHint.Val = Val;
2471 Op->PSBHint.Data = Str.data();
2472 Op->PSBHint.Length = Str.size();
2473 Op->StartLoc = S;
2474 Op->EndLoc = S;
2483 Op->BTIHint.Val = Val | 32;
2484 Op->BTIHint.Data = Str.data();
2485 Op->BTIHint.Length = Str.size();
2486 Op->StartLoc = S;
2487 Op->EndLoc = S;
2495 Op->MatrixReg.RegNum = RegNum;
2496 Op->MatrixReg.ElementWidth = ElementWidth;
2497 Op->MatrixReg.Kind = Kind;
2498 Op->StartLoc = S;
2499 Op->EndLoc = E;
2506 Op->SVCR.PStateField = PStateField;
2507 Op->SVCR.Data = Str.data();
2508 Op->SVCR.Length = Str.size();
2509 Op->StartLoc = S;
2510 Op->EndLoc = S;
2518 Op->ShiftExtend.Type = ShOp;
2519 Op->ShiftExtend.Amount = Val;
2520 Op->ShiftExtend.HasExplicitAmount = HasExplicitAmount;
2521 Op->StartLoc = S;
2522 Op->EndLoc = E;
2605 for (unsigned I = MaxBits; I > 0; --I)
2606 OS << ((RegMask & (1 << (I - 1))) >> (I - 1));
2629 /// @name Auto-generated Match Functions
2673 /// Returns an optional pair of (#elements, element-width) if Suffix
2679 std::pair<int, int> Res = {-1, -1};
2707 .Default({-1, -1});
2720 .Default({-1, -1});
2726 if (Res == std::make_pair(-1, -1))
2943 EndLoc = SMLoc::getFromPointer(getLoc().getPointer() - 1);
2991 if (Kind == Entry->getValue().first)
2992 RegNum = Entry->getValue().second;
3013 /// tryParseScalarRegister - Try to parse a register name. The token must be an
3031 /// tryParseSysCROperand - Try to parse a system instruction CR operand name.
3053 // Either an identifier for named values or a 6-bit immediate.
3070 unsigned prfop = MCE->getValue();
3075 auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(MCE->getValue());
3077 prfop, RPRFM ? RPRFM->Name : "", S, getContext()));
3089 RPRFM->Encoding, Tok.getString(), S, getContext()));
3094 /// tryParsePrefetch - Try to parse a prefetch operand.
3103 return std::optional<unsigned>(Res->Encoding);
3105 return std::optional<unsigned>(Res->Encoding);
3112 return std::optional<StringRef>(Res->Name);
3114 return std::optional<StringRef>(Res->Name);
3119 // Either an identifier for named values or a 5-bit immediate.
3130 unsigned prfop = MCE->getValue();
3135 auto PRFM = LookupByEncoding(MCE->getValue());
3154 /// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
3166 PSB->Encoding, Tok.getString(), S, getContext()));
3204 /// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
3216 BTI->Encoding, Tok.getString(), S, getContext()));
3221 /// tryParseAdrpLabel - Parse and validate a source label for the ADRP
3264 SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
3270 /// tryParseAdrLabel - Parse and validate a source label for the ADR
3300 SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
3305 /// tryParseFPImm - A floating point immediate expression operand.
3354 /// tryParseImmWithOptionalShift - Parse immediate operand, optionally with
3390 // The optional operand must be "lsl #N" where N is non-negative.
3421 /// parseCondCodeString - Parse a Condition Code string, optionally returning a
3466 /// parseCondCode - Parse a Condition Code operand.
3502 unsigned PStateImm = -1;
3506 if (SVCR->haveFeatures(getSTI().getFeatureBits()))
3507 PStateImm = SVCR->Encoding;
3531 ElementWidth = KindRes->second;
3567 unsigned ElementWidth = KindRes->second;
3583 /// tryParseOptionalShift - Some operands take an optional shift argument. Parse
3623 SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
3644 E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
3646 ShOp, MCE->getValue(), true, S, E, getContext()));
3670 {"tlb-rmi", {AArch64::FeatureTLB_RMI}},
3672 {"pan-rwv", {AArch64::FeaturePAN_RWV}},
3678 {"sve2-aes", {AArch64::FeatureSVE2AES}},
3679 {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
3680 {"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
3681 {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
3690 {"sme-f64f64", {AArch64::FeatureSMEF64F64}},
3691 {"sme-f16f16", {AArch64::FeatureSMEF16F16}},
3692 {"sme-i16i64", {AArch64::FeatureSMEI16I64}},
3720 {"sb", {AArch64::FeatureSB}},
3726 {"ssve-fp8fma", {AArch64::FeatureSSVE_FP8FMA}},
3728 {"ssve-fp8dot2", {AArch64::FeatureSSVE_FP8DOT2}},
3730 {"ssve-fp8dot4", {AArch64::FeatureSSVE_FP8DOT4}},
3732 {"sme-lutv2", {AArch64::FeatureSME_LUTv2}},
3733 {"sme-f8f16", {AArch64::FeatureSMEF8F16}},
3734 {"sme-f8f32", {AArch64::FeatureSMEF8F32}},
3735 {"sme-fa64", {AArch64::FeatureSMEFA64}},
3762 Str += "ARMv9-a";
3806 /// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
3824 else if (!IC->haveFeatures(getSTI().getFeatureBits())) {
3825 std::string Str("IC " + std::string(IC->Name) + " requires: ");
3826 setRequiredFeatureString(IC->getRequiredFeatures(), Str);
3829 createSysAlias(IC->Encoding, Operands, S);
3834 else if (!DC->haveFeatures(getSTI().getFeatureBits())) {
3835 std::string Str("DC " + std::string(DC->Name) + " requires: ");
3836 setRequiredFeatureString(DC->getRequiredFeatures(), Str);
3839 createSysAlias(DC->Encoding, Operands, S);
3844 else if (!AT->haveFeatures(getSTI().getFeatureBits())) {
3845 std::string Str("AT " + std::string(AT->Name) + " requires: ");
3846 setRequiredFeatureString(AT->getRequiredFeatures(), Str);
3849 createSysAlias(AT->Encoding, Operands, S);
3854 else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
3855 std::string Str("TLBI " + std::string(TLBI->Name) + " requires: ");
3856 setRequiredFeatureString(TLBI->getRequiredFeatures(), Str);
3859 createSysAlias(TLBI->Encoding, Operands, S);
3910 /// parseSyspAlias - The TLBIP instructions are simple aliases for
3934 TLBIorig->Name, TLBIorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
3935 TLBIorig->NeedsReg,
3937 ? TLBIorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
3938 : TLBIorig->FeaturesRequired);
3985 int64_t Value = MCE->getValue();
3996 Operands.push_back(AArch64Operand::CreateBarrier(Value, DB ? DB->Name : "",
4009 if (Mnemonic == "isb" && (!DB || DB->Encoding != AArch64DB::sy))
4012 if (Mnemonic == "tsb" && (!TSB || TSB->Encoding != AArch64TSB::csync))
4024 DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(),
4048 int64_t Value = MCE->getValue();
4049 // v8.7-A DSB in the nXS variant accepts only the following immediate
4054 Operands.push_back(AArch64Operand::CreateBarrier(DB->Encoding, DB->Name,
4070 AArch64Operand::CreateBarrier(DB->Encoding, Tok.getString(), getLoc(),
4088 if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
4089 MRSReg = SysReg->Readable ? SysReg->Encoding : -1;
4090 MSRReg = SysReg->Writeable ? SysReg->Encoding : -1;
4094 unsigned PStateImm = -1;
4096 if (PState15 && PState15->haveFeatures(getSTI().getFeatureBits()))
4097 PStateImm = PState15->Encoding;
4100 if (PState1 && PState1->haveFeatures(getSTI().getFeatureBits()))
4101 PStateImm = PState1->Encoding;
4112 /// tryParseNeonVectorRegister - Parse a vector register operand.
4129 unsigned ElementWidth = KindRes->second;
4157 Operands.push_back(AArch64Operand::CreateVectorIndex(MCE->getValue(), SIdx,
4165 // tryParseVectorRegister - Try to parse a vector register name with
4207 /// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
4223 unsigned ElementWidth = KindRes->second;
4270 /// parseRegister - Parse a register operand.
4369 unsigned &ElementWidth) -> ParseStatus {
4385 ElementWidth = KindRes->second;
4444 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg)))
4462 RegMask |= 0x1 << (RI->getEncodingValue(Reg) -
4463 RI->getEncodingValue(AArch64::ZAD0));
4479 bool NoMatchIsError) -> ParseStatus {
4510 // different types of list-operands can be matched (e.g. SVE, Neon).
4535 (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg);
4556 unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg);
4558 getContext().getRegisterInfo()->getEncodingValue(PrevReg);
4560 Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal)
4561 : (RegVal + NumRegs - PrevRegVal);
4594 /// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
4624 cast<MCConstantExpr>(ImmVal)->getValue() != 0)
4657 MCConstantExpr::create(MCE->getValue(), getContext()), StartLoc,
4697 RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,
4698 Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
4699 Ext->hasShiftExtendAmount()));
4737 MCConstantExpr::create(MCE->getValue(), getContext()), S, getLoc(),
4783 /// parseOperand - Parse a arm instruction operand. For now this parses the
4820 SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
4882 // If this is a two-word mnemonic, parse its special keyword
4894 E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
4901 // #42 -> immediate.
4928 return TokError("expected floating-point constant #0.0");
4940 E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
4961 Operands[1]->getReg());
4964 E = SMLoc::getFromPointer(Loc.getPointer() - 1);
4967 uint64_t Imm = (cast<MCConstantExpr>(SubExprVal))->getValue();
4983 // check if the immediate is an unsigned or signed 32-bit int for W regs
5004 Out = Value->getValue();
5051 Out = Reg - Base;
5073 "Testing equality of non-scalar registers not supported");
5088 /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
5114 // First check for the AArch64-specific .req directive.
5147 (Head.data() - Name.data()));
5168 (Head.data() - Name.data()) + 1);
5207 // + An '!' will indicate a pre-indexed operation.
5239 return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) ||
5240 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) ||
5241 (ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) ||
5242 (ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) ||
5243 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) ||
5244 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0));
5283 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) &&
5286 " movprfx and destination also used as non-destructive"
5292 int PgIdx = -1;
5303 if (PgIdx == -1 ||
5338 Warning(IDLoc, "register " + Twine(RI->getName(Reg)) +
5357 if (RI->isSubRegisterEq(Rn, Rt))
5360 if (RI->isSubRegisterEq(Rn, Rt2))
5411 if (RI->isSubRegisterEq(Rn, Rt))
5414 if (RI->isSubRegisterEq(Rn, Rt2))
5443 if (RI->isSubRegisterEq(Rn, Rt))
5462 if (RI->isSubRegisterEq(Rn, Rt))
5478 if (RI->isSubRegisterEq(Rt, Rs) ||
5479 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
5492 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
5493 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
5510 // Check v8.8-A memops instructions.
5755 return Error(Loc, "operand must be 64-bit form of destination register");
5757 return Error(Loc, "operand must be 32-bit form of destination register");
5795 "expected compatible register or floating-point constant");
5797 return Error(Loc, "index must be an integer in range [-32, 31].");
5799 return Error(Loc, "index must be an integer in range [-16, 15].");
5801 return Error(Loc, "index must be an integer in range [-8, 7].");
5803 return Error(Loc, "index must be a multiple of 2 in range [-16, 14].");
5805 return Error(Loc, "index must be a multiple of 3 in range [-24, 21].");
5807 return Error(Loc, "index must be a multiple of 4 in range [-32, 28].");
5809 return Error(Loc, "index must be a multiple of 16 in range [-128, 112].");
5811 return Error(Loc, "index must be a multiple of 32 in range [-256, 224].");
5813 return Error(Loc, "index must be an integer in range [-32, 31].");
5815 return Error(Loc, "index must be an integer in range [-128, 127].");
5817 return Error(Loc, "index must be an integer in range [-256, 255].");
5819 return Error(Loc, "index must be a multiple of 16 in range [-4096, 4080].");
5821 return Error(Loc, "index must be a multiple of 8 in range [-4096, 4088].");
5823 return Error(Loc, "index must be a multiple of 4 in range [-256, 252].");
5825 return Error(Loc, "index must be a multiple of 8 in range [-512, 504].");
5827 return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008].");
5950 return Error(Loc, "immediate must be an integer in range [-128, 255]"
5953 return Error(Loc, "immediate must be an integer in range [-128, 127] or a "
5954 "multiple of 256 in range [-32768, 65280]");
5957 return Error(Loc, "immediate must be an integer in range [-128, 127] or a "
5958 "multiple of 256 in range [-32768, 32512]");
5995 ComputeAvailableFeatures(STI->getFeatureBits()));
6101 return Error(Loc, "invalid restricted predicate-as-counter register "
6130 "invalid matrix operand, expected za[0-1]h.h or za[0-1]v.h");
6134 "invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s");
6138 "invalid matrix operand, expected za[0-7]h.d or za[0-7]v.d");
6142 "invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q");
6144 return Error(Loc, "invalid matrix operand, expected za[0-3].s");
6146 return Error(Loc, "invalid matrix operand, expected za[0-7].d");
6225 uint64_t Op3Val = Op3CE->getValue();
6230 NewOp3Val = (32 - Op3Val) & 0x1f;
6231 NewOp4Val = 31 - Op3Val;
6233 NewOp3Val = (64 - Op3Val) & 0x3f;
6234 NewOp4Val = 63 - Op3Val;
6249 // FIXME: Horrible hack to handle BFC->BFM alias.
6259 uint64_t LSB = LSBCE->getValue();
6260 uint64_t Width = WidthCE->getValue();
6278 ImmR = (32 - LSB) & 0x1f;
6280 ImmR = (64 - LSB) & 0x3f;
6282 uint64_t ImmS = Width - 1;
6303 // FIXME: Horrible hack to handle the BFI -> BFM, SBFIZ->SBFM, and
6304 // UBFIZ -> UBFM aliases.
6315 uint64_t Op3Val = Op3CE->getValue();
6316 uint64_t Op4Val = Op4CE->getValue();
6334 NewOp3Val = (32 - Op3Val) & 0x1f;
6336 NewOp3Val = (64 - Op3Val) & 0x3f;
6338 uint64_t NewOp4Val = Op4Val - 1;
6366 // FIXME: Horrible hack to handle the BFXIL->BFM, SBFX->SBFM, and
6367 // UBFX -> UBFM aliases.
6379 uint64_t Op3Val = Op3CE->getValue();
6380 uint64_t Op4Val = Op4CE->getValue();
6396 uint64_t NewOp4Val = Op3Val + Op4Val - 1;
6422 // The Cyclone CPU and early successors didn't execute the zero-cycle zeroing
6435 cast<MCConstantExpr>(Op3.getImm())->getValue() == 0) {
6498 // short-form NEON instructions (e.g. "fadd.2s v0, v1, v2").
6503 // If that fails, try against the alternate table containing long-form NEON:
6506 // But first, save the short-form match result: we can use it in case the
6507 // long-form match also fails.
6516 // Now, both matches failed, and the long-form match failed on the mnemonic
6517 // suffix token operand. The short-form match failure is probably more
6534 OperandLocs.push_back(Operands[i]->getStartLoc());
6967 AArch64Features.push_back(ArchInfo->ArchFeature);
6968 AArch64::getExtensionFeatures(ArchInfo->DefaultExts, AArch64Features);
7110 auto parseOp = [&]() -> bool {
7118 getTargetStreamer().emitInst(Value->getValue());
7155 if (Id <= -1U && !isValidMCLOHType(Id))
7164 if (Id == -1)
7173 assert(NbArgs != -1 && "Invalid number of arguments");
7259 if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
7417 if (check(((Reg - 19) % 2 != 0), L,
7583 EncodedReg = Reg - AArch64::X0;
7598 unsigned EncodedReg = Reg - AArch64::D0;
7615 unsigned EncodedReg = Reg - AArch64::Q0;
7647 /// ::= (_sym - 5)@AUTH(ib,123[,addr])
7680 if (Tokens[Tokens.size() - 2].isNot(AsmToken::At) ||
7681 Tokens[Tokens.size() - 1].isNot(AsmToken::Identifier) ||
7682 Tokens[Tokens.size() - 1].getIdentifier() != "AUTH")
7753 ELFRefKind = AE->getKind();
7754 Expr = AE->getSubExpr();
7760 DarwinRefKind = SE->getKind();
7766 bool Relocatable = Expr->evaluateAsRelocatable(Res, nullptr, nullptr);
7776 DarwinRefKind = Res.getSymA()->getKind();
7800 // Define this matcher function after the auto-generated include so we
7806 auto MatchesOpImmediate = [&](int64_t ExpectedVal) -> MatchResultTy {
7812 if (CE->getValue() == ExpectedVal)
7830 // matches. This is for InstAliases which have a fixed-value immediate in
7863 return MatchesOpImmediate(-N);
7881 return Error(S, "expected first even register of a consecutive same-size "
7892 return Error(S, "expected first even register of a consecutive same-size "
7896 unsigned FirstEncoding = RI->getEncodingValue(FirstReg);
7899 return Error(S, "expected first even register of a consecutive same-size "
7911 return Error(E, "expected second odd register of a consecutive same-size "
7914 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 ||
7917 return Error(E, "expected second odd register of a consecutive same-size "
7922 Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
7925 Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube32,
7955 unsigned ElementWidth = KindRes->second;
7979 RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(),
7980 getContext(), Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
7981 Ext->hasShiftExtendAmount()));
8010 Pattern = MCE->getValue();
8018 Pattern = Pat->Encoding;
8041 Pattern = Pat->Encoding;
8060 int X8Reg = RI->getMatchingSuperReg(
8065 "expected an even-numbered x-register in the range [x0,x22]");
8097 unsigned ImmFVal = cast<MCConstantExpr>(ImmF)->getValue();
8098 unsigned ImmLVal = cast<MCConstantExpr>(ImmL)->getValue();