Lines Matching defs:ElementWidth

385     int ElementWidth;
410     unsigned ElementWidth;
423     unsigned ElementWidth;
673     return MatrixReg.ElementWidth;
1288   template <int ElementWidth, unsigned Class>
1293     if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1299   template <int ElementWidth, unsigned Class>
1306          isSVEPredicateVectorRegOfWidth<ElementWidth, Class>()) &&
1307         Reg.ElementWidth == ElementWidth)
1313   template <int ElementWidth, unsigned Class>
1318     if (isSVEPredicateAsCounterReg<Class>() && (Reg.ElementWidth == ElementWidth))
1324   template <int ElementWidth, unsigned Class>
1329     if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1335   template <int ElementWidth, unsigned Class,
1339     auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1429             unsigned ElementWidth, unsigned Stride = 1>
1437     if (VectorList.ElementWidth != ElementWidth)
1445             unsigned ElementWidth>
1448         isTypedVectorList<VectorKind, NumRegs, NumElements, ElementWidth>();
1457             unsigned ElementWidth>
1460                                  ElementWidth, Stride>();
2271     Op->Reg.ElementWidth = 0;
2282   CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth,
2293     Op->Reg.ElementWidth = ElementWidth;
2299                    unsigned NumElements, unsigned ElementWidth,
2306     Op->VectorList.ElementWidth = ElementWidth;
2332                                   const unsigned ElementWidth) {
2351     if (ElementWidth == 64)
2354       std::vector<unsigned> Regs = RegMap[std::make_pair(ElementWidth, Reg)];
2492   CreateMatrixRegister(unsigned RegNum, unsigned ElementWidth, MatrixKind Kind,
2496     Op->MatrixReg.ElementWidth = ElementWidth;
3523     unsigned ElementWidth = 0;
3531       ElementWidth = KindRes->second;
3534         AArch64::ZA, ElementWidth, MatrixKind::Array, S, getLoc(),
3567   unsigned ElementWidth = KindRes->second;
3572       Reg, ElementWidth, Kind, S, getLoc(), getContext()));
4129   unsigned ElementWidth = KindRes->second;
4131       AArch64Operand::CreateVectorReg(Reg, RegKind::NeonVector, ElementWidth,
4223   unsigned ElementWidth = KindRes->second;
4225       RegNum, RK, ElementWidth, S,
4369                                 unsigned &ElementWidth) -> ParseStatus {
4385     ElementWidth = KindRes->second;
4416   unsigned FirstReg, ElementWidth;
4417   auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth);
4428   AArch64Operand::ComputeRegsForAlias(FirstReg, DRegs, ElementWidth);
4441     if (ElementWidth != NextElementWidth)
4451       AArch64Operand::ComputeRegsForAlias(Reg, DRegs, ElementWidth);
4581   unsigned ElementWidth = 0;
4584       std::tie(NumElements, ElementWidth) = *VK;
4588       FirstReg, Count, Stride, NumElements, ElementWidth, VectorKind, S,
7955   unsigned ElementWidth = KindRes->second;
7960         RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext()));
7979       RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(),