Lines Matching defs:ISD
687 {ISD::CTPOP, MVT::v2i64, 4},
688 {ISD::CTPOP, MVT::v4i32, 3},
689 {ISD::CTPOP, MVT::v8i16, 2},
690 {ISD::CTPOP, MVT::v16i8, 1},
691 {ISD::CTPOP, MVT::i64, 4},
692 {ISD::CTPOP, MVT::v2i32, 3},
693 {ISD::CTPOP, MVT::v4i16, 2},
694 {ISD::CTPOP, MVT::v8i8, 1},
695 {ISD::CTPOP, MVT::i32, 5},
699 if (const auto *Entry = CostTableLookup(CtpopCostTbl, ISD::CTPOP, MTy)) {
1530 // Bail due to missing support for ISD::STRICT_ scalable vector operations.
2481 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2482 assert(ISD && "Invalid opcode");
2523 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1}, // xtn
2524 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // xtn
2525 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1}, // xtn
2526 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1}, // xtn
2527 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 3}, // 2 xtn + 1 uzp1
2528 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1}, // xtn
2529 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2}, // 1 uzp1 + 1 xtn
2530 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1}, // 1 uzp1
2531 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1}, // 1 xtn
2532 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2}, // 1 uzp1 + 1 xtn
2533 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 4}, // 3 x uzp1 + xtn
2534 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1}, // 1 uzp1
2535 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 3}, // 3 x uzp1
2536 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 2}, // 2 x uzp1
2537 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 1}, // uzp1
2538 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 3}, // (2 + 1) x uzp1
2539 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 7}, // (4 + 2 + 1) x uzp1
2540 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2}, // 2 x uzp1
2541 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i64, 6}, // (4 + 2) x uzp1
2542 { ISD::TRUNCATE, MVT::v16i32, MVT::v16i64, 4}, // 4 x uzp1
2545 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 1 },
2546 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i32, 1 },
2547 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i64, 1 },
2548 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 1 },
2549 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i32, 1 },
2550 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i64, 2 },
2551 { ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i16, 1 },
2552 { ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i32, 3 },
2553 { ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i64, 5 },
2554 { ISD::TRUNCATE, MVT::nxv16i1, MVT::nxv16i8, 1 },
2555 { ISD::TRUNCATE, MVT::nxv2i16, MVT::nxv2i32, 1 },
2556 { ISD::TRUNCATE, MVT::nxv2i32, MVT::nxv2i64, 1 },
2557 { ISD::TRUNCATE, MVT::nxv4i16, MVT::nxv4i32, 1 },
2558 { ISD::TRUNCATE, MVT::nxv4i32, MVT::nxv4i64, 2 },
2559 { ISD::TRUNCATE, MVT::nxv8i16, MVT::nxv8i32, 3 },
2560 { ISD::TRUNCATE, MVT::nxv8i32, MVT::nxv8i64, 6 },
2563 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
2564 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
2565 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
2566 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
2567 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
2568 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
2569 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
2570 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
2571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
2572 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
2573 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
2574 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
2575 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
2576 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
2577 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
2578 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
2581 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
2582 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
2583 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
2584 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
2585 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
2586 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
2589 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
2590 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
2591 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
2592 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
2593 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
2594 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
2597 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
2598 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
2599 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
2600 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
2603 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
2604 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
2605 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
2606 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
2609 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
2610 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
2613 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
2614 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
2615 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
2616 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
2617 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
2618 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
2621 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 4 },
2622 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 4 },
2625 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
2626 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
2627 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
2628 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
2629 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
2630 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
2633 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
2634 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
2635 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
2636 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
2637 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
2638 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
2641 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
2642 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
2643 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
2644 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
2647 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f32, 1 },
2648 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f32, 1 },
2649 { ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f32, 1 },
2650 { ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f32, 1 },
2651 { ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f32, 1 },
2652 { ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f32, 1 },
2653 { ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f32, 1 },
2654 { ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f32, 1 },
2657 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
2658 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
2659 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
2660 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
2661 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
2662 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
2665 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f64, 1 },
2666 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f64, 1 },
2667 { ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f64, 1 },
2668 { ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f64, 1 },
2669 { ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f64, 1 },
2670 { ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f64, 1 },
2671 { ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f64, 1 },
2672 { ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f64, 1 },
2675 { ISD::FP_TO_SINT, MVT::nxv4i64, MVT::nxv4f32, 4 },
2676 { ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f32, 1 },
2677 { ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f32, 1 },
2678 { ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f32, 1 },
2679 { ISD::FP_TO_UINT, MVT::nxv4i64, MVT::nxv4f32, 4 },
2680 { ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f32, 1 },
2681 { ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f32, 1 },
2682 { ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f32, 1 },
2685 { ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f64, 7 },
2686 { ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f64, 7 },
2687 { ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f64, 7 },
2688 { ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f64, 7 },
2691 { ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f64, 3 },
2692 { ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f64, 3 },
2693 { ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f64, 3 },
2694 { ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f64, 3 },
2695 { ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f64, 3 },
2696 { ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f64, 3 },
2699 { ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f32, 3 },
2700 { ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f32, 3 },
2701 { ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f32, 3 },
2702 { ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f32, 3 },
2705 { ISD::FP_TO_SINT, MVT::nxv8i64, MVT::nxv8f16, 10 },
2706 { ISD::FP_TO_SINT, MVT::nxv8i32, MVT::nxv8f16, 4 },
2707 { ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f16, 1 },
2708 { ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f16, 1 },
2709 { ISD::FP_TO_UINT, MVT::nxv8i64, MVT::nxv8f16, 10 },
2710 { ISD::FP_TO_UINT, MVT::nxv8i32, MVT::nxv8f16, 4 },
2711 { ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f16, 1 },
2712 { ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f16, 1 },
2715 { ISD::FP_TO_SINT, MVT::nxv4i64, MVT::nxv4f16, 4 },
2716 { ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f16, 1 },
2717 { ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f16, 1 },
2718 { ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f16, 1 },
2719 { ISD::FP_TO_UINT, MVT::nxv4i64, MVT::nxv4f16, 4 },
2720 { ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f16, 1 },
2721 { ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f16, 1 },
2722 { ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f16, 1 },
2725 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f16, 1 },
2726 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f16, 1 },
2727 { ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f16, 1 },
2728 { ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f16, 1 },
2729 { ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f16, 1 },
2730 { ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f16, 1 },
2731 { ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f16, 1 },
2732 { ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f16, 1 },
2735 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 },
2736 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 },
2737 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 },
2740 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 },
2741 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 },
2742 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 },
2745 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 },
2746 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 },
2747 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 },
2750 { ISD::FP_EXTEND, MVT::nxv2f32, MVT::nxv2f16, 1},
2751 { ISD::FP_EXTEND, MVT::nxv4f32, MVT::nxv4f16, 1},
2752 { ISD::FP_EXTEND, MVT::nxv8f32, MVT::nxv8f16, 2},
2755 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f16, 1},
2756 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f16, 2},
2757 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f16, 4},
2760 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f32, 1},
2761 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f32, 2},
2762 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f32, 6},
2765 { ISD::BITCAST, MVT::nxv2f16, MVT::nxv2i16, 0 },
2766 { ISD::BITCAST, MVT::nxv4f16, MVT::nxv4i16, 0 },
2767 { ISD::BITCAST, MVT::nxv2f32, MVT::nxv2i32, 0 },
2770 { ISD::BITCAST, MVT::nxv2i16, MVT::nxv2f16, 0 },
2771 { ISD::BITCAST, MVT::nxv4i16, MVT::nxv4f16, 0 },
2772 { ISD::BITCAST, MVT::nxv2i32, MVT::nxv2f32, 0 },
2777 { ISD::ZERO_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},
2778 { ISD::ZERO_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},
2779 { ISD::ZERO_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},
2780 { ISD::ZERO_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},
2781 { ISD::ZERO_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},
2782 { ISD::ZERO_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},
2784 { ISD::SIGN_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},
2785 { ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},
2786 { ISD::SIGN_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},
2787 { ISD::SIGN_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},
2788 { ISD::SIGN_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},
2789 { ISD::SIGN_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},
2811 if (const auto *Entry = ConvertCostTableLookup(ConversionTbl, ISD,
2817 {ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f16, 1}, // fcvtzs
2818 {ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f16, 1},
2819 {ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f16, 1}, // fcvtzs
2820 {ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f16, 1},
2821 {ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f16, 2}, // fcvtl+fcvtzs
2822 {ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f16, 2},
2823 {ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f16, 2}, // fcvtzs+xtn
2824 {ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f16, 2},
2825 {ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f16, 1}, // fcvtzs
2826 {ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f16, 1},
2827 {ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f16, 4}, // 2*fcvtl+2*fcvtzs
2828 {ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f16, 4},
2829 {ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f16, 3}, // 2*fcvtzs+xtn
2830 {ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f16, 3},
2831 {ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f16, 2}, // 2*fcvtzs
2832 {ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f16, 2},
2833 {ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f16, 8}, // 4*fcvtl+4*fcvtzs
2834 {ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f16, 8},
2835 {ISD::UINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // ushll + ucvtf
2836 {ISD::SINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // sshll + scvtf
2837 {ISD::UINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * ushl(2) + 2 * ucvtf
2838 {ISD::SINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * sshl(2) + 2 * scvtf
2843 FP16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
2846 if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
2868 if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
3050 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3052 switch (ISD) {
3056 case ISD::SDIV:
3075 case ISD::UDIV: {
3078 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
3095 if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
3103 {ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8},
3104 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, 5},
3105 {ISD::SDIV, MVT::v4i16, 5}, {ISD::SDIV, MVT::v2i32, 1},
3106 {ISD::UDIV, MVT::v2i8, 5}, {ISD::UDIV, MVT::v4i8, 8},
3107 {ISD::UDIV, MVT::v8i8, 8}, {ISD::UDIV, MVT::v2i16, 5},
3108 {ISD::UDIV, MVT::v4i16, 5}, {ISD::UDIV, MVT::v2i32, 1}};
3110 const auto *Entry = CostTableLookup(DivTbl, ISD, VT.getSimpleVT());
3148 case ISD::MUL:
3169 case ISD::ADD:
3170 case ISD::XOR:
3171 case ISD::OR:
3172 case ISD::AND:
3173 case ISD::SRL:
3174 case ISD::SRA:
3175 case ISD::SHL:
3180 case ISD::FNEG:
3181 case ISD::FADD:
3182 case ISD::FSUB:
3191 case ISD::FMUL:
3192 case ISD::FDIV:
3200 case ISD::FREM:
3239 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3242 if (isa<FixedVectorType>(ValTy) && ISD == ISD::SELECT) {
3274 { ISD::SELECT, MVT::v2i1, MVT::v2f32, 2 },
3275 { ISD::SELECT, MVT::v2i1, MVT::v2f64, 2 },
3276 { ISD::SELECT, MVT::v4i1, MVT::v4f32, 2 },
3277 { ISD::SELECT, MVT::v4i1, MVT::v4f16, 2 },
3278 { ISD::SELECT, MVT::v8i1, MVT::v8f16, 2 },
3279 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 },
3280 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
3281 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
3282 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
3283 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
3284 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
3290 if (const auto *Entry = ConvertCostTableLookup(VectorSelectTbl, ISD,
3297 if (isa<FixedVectorType>(ValTy) && ISD == ISD::SETCC) {
3307 if (ValTy->isIntegerTy() && ISD == ISD::SETCC && I &&
3850 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3851 assert(ISD && "Invalid opcode");
3853 switch (ISD) {
3854 case ISD::ADD:
3855 case ISD::AND:
3856 case ISD::OR:
3857 case ISD::XOR:
3858 case ISD::FADD:
3901 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3902 assert(ISD && "Invalid opcode");
3913 {ISD::ADD, MVT::v8i8, 2},
3914 {ISD::ADD, MVT::v16i8, 2},
3915 {ISD::ADD, MVT::v4i16, 2},
3916 {ISD::ADD, MVT::v8i16, 2},
3917 {ISD::ADD, MVT::v4i32, 2},
3918 {ISD::ADD, MVT::v2i64, 2},
3919 {ISD::OR, MVT::v8i8, 15},
3920 {ISD::OR, MVT::v16i8, 17},
3921 {ISD::OR, MVT::v4i16, 7},
3922 {ISD::OR, MVT::v8i16, 9},
3923 {ISD::OR, MVT::v2i32, 3},
3924 {ISD::OR, MVT::v4i32, 5},
3925 {ISD::OR, MVT::v2i64, 3},
3926 {ISD::XOR, MVT::v8i8, 15},
3927 {ISD::XOR, MVT::v16i8, 17},
3928 {ISD::XOR, MVT::v4i16, 7},
3929 {ISD::XOR, MVT::v8i16, 9},
3930 {ISD::XOR, MVT::v2i32, 3},
3931 {ISD::XOR, MVT::v4i32, 5},
3932 {ISD::XOR, MVT::v2i64, 3},
3933 {ISD::AND, MVT::v8i8, 15},
3934 {ISD::AND, MVT::v16i8, 17},
3935 {ISD::AND, MVT::v4i16, 7},
3936 {ISD::AND, MVT::v8i16, 9},
3937 {ISD::AND, MVT::v2i32, 3},
3938 {ISD::AND, MVT::v4i32, 5},
3939 {ISD::AND, MVT::v2i64, 3},
3941 switch (ISD) {
3944 case ISD::ADD:
3945 if (const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy))
3948 case ISD::XOR:
3949 case ISD::AND:
3950 case ISD::OR:
3951 const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy);