Lines Matching +full:use +full:- +full:case
1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "aarch64-subtarget"
39 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
42 // If OS supports TBI, use this flag to enable it.
44 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
48 "aarch64-macho-enable-nonlazybind",
49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),
52 static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
53 cl::desc("Enable the use of AA during codegen."));
56 "aarch64-insert-extract-base-cost",
63 ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "
69 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",
76 "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden,
77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));
88 // Determine default and user-specified characteristics
107 case Others:
109 case Carmel:
112 case CortexA35:
113 case CortexA53:
114 case CortexA55:
115 case CortexR82:
116 case CortexR82AE:
121 case CortexA57:
127 case CortexA65:
130 case CortexA72:
131 case CortexA73:
132 case CortexA75:
137 case CortexA76:
138 case CortexA77:
139 case CortexA78:
140 case CortexA78AE:
141 case CortexA78C:
142 case CortexX1:
147 case CortexA510:
148 case CortexA520:
154 case CortexA710:
155 case CortexA715:
156 case CortexA720:
157 case CortexA725:
158 case CortexX2:
159 case CortexX3:
160 case CortexX4:
161 case CortexX925:
167 case A64FX:
177 case AppleA7:
178 case AppleA10:
179 case AppleA11:
180 case AppleA12:
181 case AppleA13:
182 case AppleA14:
183 case AppleA15:
184 case AppleA16:
185 case AppleA17:
186 case AppleM4:
192 case AppleA14:
193 case AppleA15:
194 case AppleA16:
195 case AppleA17:
196 case AppleM4:
203 case ExynosM3:
209 case Falkor:
211 // FIXME: remove this to enable 64-bit SLP if performance looks good.
218 case Kryo:
225 // FIXME: remove this to enable 64-bit SLP if performance looks good.
228 case NeoverseE1:
231 case NeoverseN1:
236 case NeoverseN2:
237 case NeoverseN3:
238 case NeoverseV2:
239 case NeoverseV3:
245 case NeoverseV1:
252 case Neoverse512TVB:
257 case Saphira:
259 // FIXME: remove this to enable 64-bit SLP if performance looks good.
262 case ThunderX2T99:
270 // FIXME: remove this to enable 64-bit SLP if performance looks good.
273 case ThunderX:
274 case ThunderXT88:
275 case ThunderXT81:
276 case ThunderXT83:
280 // FIXME: remove this to enable 64-bit SLP if performance looks good.
283 case TSV110:
288 case ThunderX3T110:
296 // FIXME: remove this to enable 64-bit SLP if performance looks good.
299 case Ampere1:
300 case Ampere1A:
301 case Ampere1B:
307 case Oryon:
358 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))
361 // X30 is named LR, so we can't use TRI->getName to check X30.
364 // X29 is named FP, so we can't use TRI->getName to check X29.
396 // MachO large model always goes via a GOT, simply to get a single 8-byte
405 if (GV->isTagged())
409 if (GV->hasDLLImportStorageClass()) {
417 // The small code model's direct accesses use ADRP, which cannot
421 GV->hasExternalWeakLinkage())
428 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
439 !GV->hasInternalLinkage())
445 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))
449 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {
450 if (GV->hasDLLImportStorageClass()) {
452 // directly, use MO_ARM64EC_CALLMANGLE.
456 if (GV->hasExternalLinkage()) {
457 // If we're calling a symbol directly, use the mangled form in the
463 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.
473 // bi-directional scheduling. 253.perlbmk.
477 // help nearly no benchmark on out-of-order architectures, on the other hand
483 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,
486 !Def->isInstr() || !Use->isInstr() ||
487 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
488 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
493 const MachineInstr *DefMI = Def->getInstr();
494 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {
495 Register Reg = DefMI->getOperand(DefOpIdx).getReg();
504 // If the Use is a BUNDLE, find the first instruction that uses the Reg.
505 const MachineInstr *UseMI = Use->getInstr();
506 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {
507 Register Reg = UseMI->getOperand(UseOpIdx).getReg();
518 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx));
572 if (MF.getFunction().hasFnAttribute("ptrauth-returns") &&
573 MF.getFunction().hasFnAttribute("ptrauth-auth-traps"))
578 // At now, use None by default because checks may introduce an unexpected
579 // performance regression or incompatibility with execute-only mappings.
586 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))