Lines Matching full:latency

16 // uops. Now, the latency spreadsheet has information based on fragmented uops,
22   let LoadLatency       =   4; // Optimistic load latency
63 // Map the target-defined scheduler read/write resources and latency for
66 def : WriteRes<WriteImm,   [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteI,     [KryoUnitXY]> { let Latency = 1; }
69       { let Latency = 2; let NumMicroOps = 2; }
71       { let Latency = 2; let NumMicroOps = 2; }
73       { let Latency = 2; let NumMicroOps = 2; }
74 def : WriteRes<WriteIS,    [KryoUnitXY]> { let Latency = 2; }
76       { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
78       { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
79 def : WriteRes<WriteIM32,  [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM64,  [KryoUnitX]> { let Latency = 5; }
81 def : WriteRes<WriteBr,    [KryoUnitXY]> { let Latency = 1; }
82 def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; }
83 def : WriteRes<WriteLD,    [KryoUnitLS]> { let Latency = 4; }
84 def : WriteRes<WriteST,    [KryoUnitLS]> { let Latency = 4; }
85 def : WriteRes<WriteSTP,   [KryoUnitLS]> { let Latency = 4; }
86 def : WriteRes<WriteAdr,   [KryoUnitXY]> { let Latency = 6; }
87 def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; }
88 def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; }
90       { let Latency = 3; let NumMicroOps = 2; }
91 def : WriteRes<WriteFCmp,  [KryoUnitXY]> { let Latency = 2; }
92 def : WriteRes<WriteFCvt,  [KryoUnitX]> { let Latency = 4; }
93 def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; }
94 def : WriteRes<WriteFImm,  [KryoUnitXY]> { let Latency = 6; }
96       { let Latency = 6; let NumMicroOps = 2; }
98       { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
99 def : WriteRes<WriteVd,    [KryoUnitXY]> { let Latency = 6; }
100 def : WriteRes<WriteVq,    [KryoUnitXY]> { let Latency = 6; }
101 def : WriteRes<WriteVLD,   [KryoUnitLS]> { let Latency = 4; }
102 def : WriteRes<WriteVST,   [KryoUnitLS]> { let Latency = 4; }
104 def : WriteRes<WriteSys,     []> { let Latency = 1; }
105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
106 def : WriteRes<WriteHint,    []> { let Latency = 1; }
108 def : WriteRes<WriteLDHi,    []> { let Latency = 4; }