Lines Matching full:latency
136 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
142 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
143 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
144 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
146 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
150 M5UnitE]> { let Latency = 2;
154 M5UnitC]> { let Latency = 3;
157 M5UnitC]> { let Latency = 2;
159 def M5WriteAFW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
161 def M5WriteAFX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
190 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
194 def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
195 def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
196 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
199 def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
201 def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
204 def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
206 def M5WriteL4 : SchedWriteRes<[M5UnitL]> { let Latency = 4; }
207 def M5WriteL5 : SchedWriteRes<[M5UnitL]> { let Latency = 5; }
208 def M5WriteL6 : SchedWriteRes<[M5UnitL]> { let Latency = 6; }
210 M5UnitL]> { let Latency = 6;
213 M5UnitL]> { let Latency = 6;
217 M5UnitL]> { let Latency = 6;
220 M5UnitL]> { let Latency = 4;
223 M5UnitL]> { let Latency = 7;
229 M5UnitL]> { let Latency = 15;
236 M5UnitL]> { let Latency = 15;
240 M5UnitL]> { let Latency = 13;
244 M5UnitL]> { let Latency = 13;
247 def M5WriteLH : SchedWriteRes<[]> { let Latency = 6;
254 def M5WriteS1 : SchedWriteRes<[M5UnitS]> { let Latency = 1; }
255 def M5WriteSA : SchedWriteRes<[M5UnitS0]> { let Latency = 4; }
257 M5UnitS]> { let Latency = 2;
270 M5UnitS0]> { let Latency = 5;
273 M5UnitS0]> { let Latency = 2;
276 M5UnitNSHF]> { let Latency = 6;
280 M5UnitS0]> { let Latency = 5;
283 M5UnitNMSC]> { let Latency = 5;
288 M5UnitNMSC]> { let Latency = 8;
293 M5UnitFCVT]> { let Latency = 7;
296 M5UnitC]> { let Latency = 3;
299 M5UnitFSQR]> { let Latency = 7;
302 M5UnitFDIV]> { let Latency = 7;
305 M5UnitFDIV]> { let Latency = 12;
308 M5UnitFSQR]> { let Latency = 8;
311 M5UnitFSQR]> { let Latency = 12;
316 def M5WriteFADD2 : SchedWriteRes<[M5UnitFADD]> { let Latency = 2; }
318 def M5WriteFCVT2 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 2; }
319 def M5WriteFCVT2A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 2; }
320 def M5WriteFCVT3 : SchedWriteRes<[M5UnitFCVT]> { let Latency = 3; }
321 def M5WriteFCVT3A : SchedWriteRes<[M5UnitFCVT0]> { let Latency = 3; }
323 M5UnitS0]> { let Latency = 3;
326 M5UnitS0]> { let Latency = 4;
329 M5UnitS0]> { let Latency = 6;
332 def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5;
334 def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7;
336 def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12;
339 def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; }
340 def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; }
342 def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5;
344 def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7;
346 def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8;
348 def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12;
351 def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; }
352 def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; }
354 def M5WriteNDOT2 : SchedWriteRes<[M5UnitNDOT]> { let Latency = 2; }
356 def M5WriteNCRY2 : SchedWriteRes<[M5UnitNCRY]> { let Latency = 2; }
357 def M5WriteNCRY1A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 1; }
358 def M5WriteNCRY2A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 2; }
359 def M5WriteNCRY3A : SchedWriteRes<[M5UnitNCRY0]> { let Latency = 3; }
360 def M5WriteNCRY5A : SchedWriteRes<[M5UnitNCRY]> { let Latency = 5; }
362 def M5WriteNHAD1 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 1; }
363 def M5WriteNHAD3 : SchedWriteRes<[M5UnitNHAD]> { let Latency = 3; }
365 def M5WriteNMSC1 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 1; }
366 def M5WriteNMSC2 : SchedWriteRes<[M5UnitNMSC]> { let Latency = 2; }
368 def M5WriteNMUL3 : SchedWriteRes<[M5UnitNMUL]> { let Latency = 3; }
370 def M5WriteNSHF1 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 1; }
371 def M5WriteNSHF2 : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; }
372 def M5WriteNSHFA : SchedWriteRes<[M5UnitNSHF]> { let Latency = 2; }
373 def M5WriteNSHFB : SchedWriteRes<[M5UnitNSHF]> { let Latency = 4;
375 def M5WriteNSHFC : SchedWriteRes<[M5UnitNSHF]> { let Latency = 6;
377 def M5WriteNSHFD : SchedWriteRes<[M5UnitNSHF]> { let Latency = 8;
380 def M5WriteNSHT2 : SchedWriteRes<[M5UnitNSHT]> { let Latency = 2; }
381 def M5WriteNSHT4A : SchedWriteRes<[M5UnitNSHT1]> { let Latency = 4; }
384 M5UnitL]> { let Latency = 6;
388 M5UnitL]> { let Latency = 7;
393 M5UnitL]> { let Latency = 7;
396 M5UnitNSHF]> { let Latency = 7;
400 M5UnitL]> { let Latency = 11;
405 M5UnitNSHF]> { let Latency = 7;
410 M5UnitL]> { let Latency = 13;
415 M5UnitNSHF]> { let Latency = 8;
421 M5UnitNSHF]> { let Latency = 8;
427 M5UnitNSHF]> { let Latency = 8;
434 M5UnitNSHF]> { let Latency = 8;
439 M5UnitL]> { let Latency = 15;
444 M5UnitFST]> { let Latency = 1;
449 M5UnitFST]> { let Latency = 2;
456 M5UnitFST]> { let Latency = 3;
465 M5UnitFST]> { let Latency = 4;
468 M5UnitFST]> { let Latency = 2; }
472 M5UnitFST]> { let Latency = 2;
477 M5UnitFST]> { let Latency = 4;
485 M5UnitFST]> { let Latency = 4;
488 M5UnitFST]> { let Latency = 1;
501 M5UnitFST]> { let Latency = 8;
506 M5UnitFST]> { let Latency = 1;
510 M5UnitFST]> { let Latency = 3;
517 M5UnitFST]> { let Latency = 4;
600 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
601 def : WriteRes<WriteHint, []> { let Latency = 1; }
602 def : WriteRes<WriteSys, []> { let Latency = 1; }