Lines Matching defs:MF
71 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
72 assert(MF && "Invalid MachineFunction pointer.");
74 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
78 if (MF->getFunction().getCallingConv() == CallingConv::PreserveNone)
80 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
83 if (MF->getFunction().getCallingConv() == CallingConv::ARM64EC_Thunk_X64)
88 if (MF->getSubtarget<AArch64Subtarget>().isTargetDarwin())
89 return getDarwinCalleeSavedRegs(MF);
91 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check)
93 if (MF->getSubtarget<AArch64Subtarget>().isTargetWindows()) {
94 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
96 MF->getFunction().getAttributes().hasAttrSomewhere(
99 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail)
103 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
105 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
107 if (MF->getFunction().getCallingConv() ==
114 if (MF->getFunction().getCallingConv() ==
121 if (MF->getFunction().getCallingConv() ==
128 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
130 MF->getFunction().getAttributes().hasAttrSomewhere(
133 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail)
135 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
137 if (MF->getFunction().getCallingConv() == CallingConv::PreserveAll)
139 if (MF->getFunction().getCallingConv() == CallingConv::Win64)
143 if (MF->getInfo<AArch64FunctionInfo>()->isSVECC())
149 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const {
150 assert(MF && "Invalid MachineFunction pointer.");
151 assert(MF->getSubtarget<AArch64Subtarget>().isTargetDarwin() &&
154 if (MF->getFunction().getCallingConv() == CallingConv::CFGuard_Check)
157 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
159 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
162 if (MF->getFunction().getCallingConv() ==
169 if (MF->getFunction().getCallingConv() ==
176 if (MF->getFunction().getCallingConv() ==
183 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
184 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()
187 if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
189 MF->getFunction().getAttributes().hasAttrSomewhere(
192 if (MF->getFunction().getCallingConv() == CallingConv::SwiftTail)
194 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
196 if (MF->getFunction().getCallingConv() == CallingConv::PreserveAll)
198 if (MF->getFunction().getCallingConv() == CallingConv::Win64)
204 const MachineFunction *MF) const {
205 assert(MF && "Invalid MachineFunction pointer.");
206 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
207 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
213 MachineFunction &MF) const {
214 const MCPhysReg *CSRs = getCalleeSavedRegs(&MF);
220 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
226 MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
243 AArch64RegisterInfo::getDarwinCallPreservedMask(const MachineFunction &MF,
245 assert(MF.getSubtarget<AArch64Subtarget>().isTargetDarwin() &&
264 if (MF.getSubtarget<AArch64Subtarget>()
267 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
279 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
281 bool SCS = MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack);
292 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
295 return getDarwinCallPreservedMask(MF, CC);
311 if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
313 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
332 const MachineFunction &MF) const {
333 if (MF.getSubtarget<AArch64Subtarget>().isTargetLinux())
347 void AArch64RegisterInfo::UpdateCustomCallPreservedMask(MachineFunction &MF,
349 uint32_t *UpdatedMask = MF.allocateRegMask();
354 if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
380 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
390 if (MF.getSubtarget<AArch64Subtarget>().isTargetDarwin())
400 AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
402 if (hasBasePointer(MF) && MCRegisterInfo::regsOverlap(PhysReg, AArch64::X19))
405 if (MF.getSubtarget<AArch64Subtarget>().isWindowsArm64EC()) {
427 AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
428 const AArch64FrameLowering *TFI = getFrameLowering(MF);
435 if (TFI->hasFP(MF) || TT.isOSDarwin())
438 if (MF.getSubtarget<AArch64Subtarget>().isWindowsArm64EC()) {
451 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
455 if (hasBasePointer(MF))
459 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening))
463 if (MF.getSubtarget<AArch64Subtarget>().hasSVE())
467 if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
475 if (MF.getSubtarget<AArch64Subtarget>().hasSME2()) {
484 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
496 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
497 BitVector Reserved = getStrictlyReservedRegs(MF);
500 if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReservedForRA(i))
504 if (MF.getSubtarget<AArch64Subtarget>().isLRReservedForRA()) {
510 if (!MF.getProperties().hasProperty(
519 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
521 return getReservedRegs(MF)[Reg];
524 bool AArch64RegisterInfo::isStrictlyReservedReg(const MachineFunction &MF,
526 return getStrictlyReservedRegs(MF)[Reg];
529 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
530 return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
531 return isStrictlyReservedReg(MF, r);
536 const MachineFunction &MF) const {
537 const Function &F = MF.getFunction();
542 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
547 if (MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening) &&
555 return !isReservedReg(MF, PhysReg);
559 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
573 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
574 const MachineFrameInfo &MFI = MF.getFrameInfo();
584 if (MFI.hasVarSizedObjects() || MF.hasEHFunclets()) {
585 if (hasStackRealignment(MF))
588 auto &ST = MF.getSubtarget<AArch64Subtarget>();
590 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
610 bool AArch64RegisterInfo::isArgumentRegister(const MachineFunction &MF,
612 CallingConv::ID CC = MF.getFunction().getCallingConv();
613 const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
614 bool IsVarArg = STI.isCallingConvWin64(MF.getFunction().getCallingConv(),
615 MF.getFunction().isVarArg());
627 if (!MF.getFunction().isVarArg())
691 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
692 const AArch64FrameLowering *TFI = getFrameLowering(MF);
693 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
697 const MachineFunction &MF) const {
702 const MachineFunction &MF) const {
707 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
716 const AArch64FrameLowering &TFI = *getFrameLowering(MF);
717 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
718 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() ||
721 return TFI.hasFP(MF) && !hasStackRealignment(MF) && !AFI->getStackSizeSVE();
725 const MachineFunction &MF) const {
730 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
731 const MachineFrameInfo &MFI = MF.getFrameInfo();
732 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
764 MachineFunction &MF = *MI->getParent()->getParent();
765 const AArch64FrameLowering *TFI = getFrameLowering(MF);
766 MachineFrameInfo &MFI = MF.getFrameInfo();
786 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
823 const MachineFunction &MF = *MBB->getParent();
825 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
829 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
851 const MachineFunction *MF = MI.getParent()->getParent();
853 MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
922 MachineFunction &MF = *MBB.getParent();
923 const MachineFrameInfo &MFI = MF.getFrameInfo();
925 MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
926 const AArch64FrameLowering *TFI = getFrameLowering(MF);
937 TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
948 StackOffset Offset = TFI->getNonLocalFrameIndexReference(MF, FrameIndex);
958 const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
971 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
973 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
989 MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
1009 MachineFunction &MF) const {
1010 const AArch64FrameLowering *TFI = getFrameLowering(MF);
1024 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
1025 - MF.getSubtarget<AArch64Subtarget>().getNumXRegisterReserved()
1026 - hasBasePointer(MF); // X19
1056 const MachineFunction &MF) const {
1057 const auto &MFI = MF.getFrameInfo();
1058 if (!MF.hasEHFunclets() && !MFI.hasVarSizedObjects())
1060 else if (hasStackRealignment(MF))
1062 return getFrameRegister(MF);