Lines Matching defs:MOP
833 bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) {
834 return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
835 TRI->regsOverlap(MOP.getReg(), DefReg);
848 for (const MachineOperand &MOP : phys_regs_and_masks(MI))
849 if (MOP.isReg() && MOP.isKill())
850 Units.removeReg(MOP.getReg());
852 for (const MachineOperand &MOP : phys_regs_and_masks(MI))
853 if (MOP.isReg() && !MOP.isKill())
854 Units.addReg(MOP.getReg());
901 MachineOperand &MOP = MI.getOperand(OpIdx);
904 if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
906 (MOP.isDef() && MOP.isImplicit())) &&
907 TRI->regsOverlap(MOP.getReg(), RegToRename)) {
908 assert((MOP.isImplicit() ||
909 (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
919 TRI->getMinimalPhysRegClass(MOP.getReg()));
921 MOP.setReg(MatchingReg);
927 MachineOperand &MOP = MI.getOperand(OpIdx);
928 if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
929 TRI->regsOverlap(MOP.getReg(), RegToRename)) {
930 assert((MOP.isImplicit() ||
931 (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
939 TRI->getMinimalPhysRegClass(MOP.getReg()));
942 MOP.setReg(MatchingReg);
969 [this, RegToCheck](const MachineOperand &MOP) {
970 return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
971 MOP.isUndef() ||
972 !TRI->regsOverlap(MOP.getReg(), RegToCheck);
1127 for (const MachineOperand &MOP : phys_regs_and_masks(*I))
1128 if (MOP.isReg() && MOP.isKill())
1129 DefinedInBB.addReg(MOP.getReg());
1422 static bool canRenameMOP(const MachineOperand &MOP,
1424 if (MOP.isReg()) {
1425 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());
1436 << MOP << ")\n");
1443 if (MOP.isImplicit() && MOP.isDef()) {
1444 if (!isRewritableImplicitDef(MOP.getParent()->getOpcode()))
1447 MOP.getParent()->getOperand(0).getReg(), MOP.getReg());
1450 return MOP.isImplicit() ||
1451 (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
1468 [TRI, RegToRename](const MachineOperand &MOP) {
1469 return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
1470 MOP.isImplicit() && MOP.isKill() &&
1471 TRI->regsOverlap(RegToRename, MOP.getReg());
1513 for (auto &MOP : MI.operands()) {
1514 if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||
1515 !TRI->regsOverlap(MOP.getReg(), RegToRename))
1517 if (!canRenameMOP(MOP, TRI)) {
1518 LLVM_DEBUG(dbgs() << " Cannot rename " << MOP << " in " << MI);
1521 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
1525 for (auto &MOP : MI.operands()) {
1526 if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
1527 !TRI->regsOverlap(MOP.getReg(), RegToRename))
1530 if (!canRenameMOP(MOP, TRI)) {
1531 LLVM_DEBUG(dbgs() << " Cannot rename " << MOP << " in " << MI);
1534 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
1580 for (auto &MOP : MI.operands()) {
1581 if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
1582 !TRI->regsOverlap(MOP.getReg(), RegToRename))
1584 if (!canRenameMOP(MOP, TRI)) {
1585 LLVM_DEBUG(dbgs() << " Cannot rename " << MOP << " in " << MI);
1588 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));