Lines Matching defs:LdSt

2700     const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2703   if (!LdSt.mayLoadOrStore())
2708   if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable,
3491     const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
3494   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
3496   if (LdSt.getNumExplicitOperands() == 3) {
3498     if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
3499         !LdSt.getOperand(2).isImm())
3501   } else if (LdSt.getNumExplicitOperands() == 4) {
3503     if (!LdSt.getOperand(1).isReg() ||
3504         (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
3505         !LdSt.getOperand(3).isImm())
3516   if (!getMemOpInfo(LdSt.getOpcode(), Scale, Width, Dummy1, Dummy2))
3522   if (LdSt.getNumExplicitOperands() == 3) {
3523     BaseOp = &LdSt.getOperand(1);
3524     Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinValue();
3526     assert(LdSt.getNumExplicitOperands() == 4 && "invalid number of operands");
3527     BaseOp = &LdSt.getOperand(2);
3528     Offset = LdSt.getOperand(3).getImm() * Scale.getKnownMinValue();
3539 AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const {
3540   assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
3541   MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
4310 /// Only called for LdSt for which getMemOperandWithOffset returns true.