Lines Matching defs:TBL
140 cl::desc("Combine ext and trunc to TBL"),
2694 MAKE_CASE(AArch64ISD::TBL)
5762 return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(),
12023 // We need a v16i8 for TBL, so we extend the source with a placeholder vector
12031 // Preconditions met, so we can use a vector (AND +) TBL to build this vector.
12106 // If we have 3 or 4 sources, try to generate a TBL, which will at least be
12847 // Check to see if we can use the TBL instruction.
13385 SDValue TBL = DAG.getNode(AArch64ISD::TBL, DL, MVT::nxv2i64, V, ShuffleMask);
13386 return DAG.getNode(ISD::BITCAST, DL, VT, TBL);
16292 "TBL lowering is not supported for a conversion instruction with this "
16389 "Maximum elements selected using TBL instruction cannot exceed 16!");
16396 // Create TBL's table of bytes in 1,2,3 or 4 FP/SIMD registers using shuffles
16397 // over the source vector. If TBL's maximum 4 FP/SIMD registers are saturated,
16398 // call TBL & save the result in a vector of TBL results for combining later.
16417 "Lowering trunc for vectors requiring different TBL instructions is "
16419 // Call TBL for the residual table bytes present in 1,2, or 3 FP/SIMD
16440 // Extract the destination vector from TBL result(s) after combining them
28096 // TBL mask element needs adjustment.
28325 // Avoid producing TBL instruction if we don't know SVE register minimal size,