Lines Matching defs:SetCC

19003   SDValue SetCC = N->getOperand(0);
19015   if (SetCC.getOpcode() == ISD::SETCC &&
19016       SetCC.getOperand(0).getValueType() == MVT::f32) {
19724 /// Helper structure to keep track of SetCC information.
19730 /// Helper structure to be able to read SetCC information.  If set to
21558   const SDValue SetCC = N->getOperand(0);
21560   const SDValue CCOp0 = SetCC.getOperand(0);
21561   const SDValue CCOp1 = SetCC.getOperand(1);
21567       cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get();
21572   if (isCheapToExtend(SetCC.getOperand(0)) &&
21573       isCheapToExtend(SetCC.getOperand(1))) {
21580         SDLoc(SetCC), N->getValueType(0), Ext1, Ext2,
21581         cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get());
23812 // Try to re-use an already extended operand of a vector SetCC feeding a
23821   // the result type has a larger element type than the SetCC operand.
24171   SDValue SetCC = N->getOperand(0);
24172   if (SetCC.getOpcode() != ISD::SETCC || !SetCC.hasOneUse())
24186   ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
24188       ISD::getSetCCInverse(CC, SetCC.getOperand(0).getValueType());
24190       DAG.getSetCC(SDLoc(SetCC), SetCC.getValueType(), SetCC.getOperand(0),
24191                    SetCC.getOperand(1), InverseCC);
24218   SDValue SetCC = N->getOperand(0);
24219   if (SetCC.getOpcode() == ISD::SETCC &&
24220       SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) {
24221     SDValue CmpLHS = SetCC.getOperand(0);
24223     SDNode *CmpRHS = SetCC.getOperand(1).getNode();
24262   SetCC = DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
24265   return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
24327   SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
24331   SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask);