Lines Matching defs:SUB
1089 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP,
2100 setOperationAction(ISD::SUB, VT, Default);
3428 return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
3480 } else if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
3586 } else if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
5069 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5080 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5128 RMValue = DAG.getNode(ISD::SUB, DL, MVT::i32, RMValue,
6600 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
6998 case ISD::SUB:
7750 FIN = DAG.getNode(ISD::SUB, DL, MVT::i64, Val,
10510 } else if (TVal.getOpcode() == ISD::SUB) {
10511 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
11433 // J - Constant that can be used with a SUB instruction
11832 // The I constraint applies only to simple ADD or SUB immediate operands:
11834 // The J constraint applies only to ADD or SUB immediates that would be
11835 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
14703 Res = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Res);
14946 SDValue NegShift = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
15379 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
15416 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
15444 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
17656 if (ABS->getOperand(0)->getOpcode() != ISD::SUB ||
17660 SDValue SUB = ABS->getOperand(0);
17661 unsigned Opcode0 = SUB->getOperand(0).getOpcode();
17662 unsigned Opcode1 = SUB->getOperand(1).getOpcode();
17664 if (SUB->getOperand(0)->getValueType(0) != MVT::v16i32 ||
17665 SUB->getOperand(1)->getValueType(0) != MVT::v16i32)
17677 SDValue EXT0 = SUB->getOperand(0);
17678 SDValue EXT1 = SUB->getOperand(1);
18269 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) {
18272 if (AddSubOpc == ISD::SUB)
18327 N->use_begin()->getOpcode() == ISD::SUB))
18352 return DAG.getNode(ISD::SUB, DL, VT, N0, N1);
18358 return DAG.getNode(ISD::SUB, DL, VT, Zero, N);
18684 // Find a SUB and an ADD operand, one from each AND.
18685 if (O0.getOpcode() == ISD::SUB && O1.getOpcode() == ISD::ADD) {
18690 } else if (O0.getOpcode() == ISD::ADD && O1.getOpcode() == ISD::SUB) {
19982 return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0));
19989 return DAG.getNode(ISD::SUB, DL, VT, Zero, Op);
20320 static SDValue performAddCombineSubShift(SDNode *N, SDValue SUB, SDValue Z,
20333 if (SUB.getOpcode() != ISD::SUB || !SUB.hasOneUse())
20336 SDValue Shift = SUB.getOperand(0);
20343 SDValue Y = SUB.getOperand(1);
20344 SDValue NewSub = DAG.getNode(ISD::SUB, DL, VT, Z, Y);
20350 // NOTE: Swapping LHS and RHS is not done for SUB, since SUB is not
20390 if (N->getOpcode() != ISD::SUB)
20413 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, X, M1);
20414 return DAG.getNode(ISD::SUB, SDLoc(N), VT, Sub, M2);
20434 if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::SUB)
20605 case ISD::SUB:
20643 if (Shift.getOpcode() != ISD::SHL && N->getOpcode() != ISD::SUB)
21397 return DAG.getNode(ISD::SUB, SDLoc(N), N->getValueType(0), N->getOperand(2),
21400 return convertMergedOpToPredOp(N, ISD::SUB, DAG, true, true);
24440 return DAG.getNode(ISD::SUB, DL, MVT::i64, Result,
25267 case ISD::SUB:
25665 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
25699 if (Op->getOpcode() == ISD::SUB)
27405 Res = DAG.getNode(ISD::SUB, dl, ContainerVT,