Lines Matching defs:Pg
14698 SDValue Pg = getPredicateForScalableVector(DAG, dl, VT);
14700 DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, VT, Pg, Op->getOperand(0),
19147 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
19193 SDValue Pg = getPTrue(DAG, SDLoc(N), VT, AArch64SVEPredPattern::all);
19194 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::FIRST_ACTIVE);
19230 SDValue Pg = getPTrue(DAG, SDLoc(N), OpVT, AArch64SVEPredPattern::all);
19231 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE);
21057 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
21065 assert(Op.getValueType() == Pg.getValueType() &&
21077 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Pg);
21079 Pg = getSVEPredicateBitCast(MVT::nxv16i1, Pg, DAG);
21086 DL, MVT::Other, Pg, Op);
21162 SDValue Pg = N->getOperand(1);
21167 if (isAllActivePredicate(DAG, Pg)) {
21171 return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg, Op1, Op2);
21697 N->getOperand(2), // Pg
21776 N->getOperand(3), // Pg
22336 SDValue Pg = N->getOperand(1);
22358 if (ExtPg == Pg && ExtFromEVT == MVT::i32) {
22366 {Chain, Pg, Base, UnextendedOffset, Ty});
24607 N->getOperand(3), // Pg
24704 N->getOperand(2), // Pg
27236 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
27244 LoadVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(), Pg,
27255 Pg, Result, DAG.getUNDEF(ContainerVT));
27271 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
27274 return Pg;
27279 return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, Pg.getValueType(),
27280 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)});
27344 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
27351 NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg,
27363 Store->getBasePtr(), Store->getOffset(), Pg, MemVT,
27401 SDValue Pg = getPredicateForFixedLengthVector(DAG, dl, VT);
27403 DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, ContainerVT, Pg, Op1, Op2);
27560 auto Pg = getPredicateForVector(DAG, DL, VT);
27567 SmallVector<SDValue, 4> Operands = {Pg};
27595 SmallVector<SDValue, 4> Operands = {Pg};
27655 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
27664 Pg, AccOp, VecOp);
27679 SDValue Pg = getPredicateForVector(DAG, DL, OpVT);
27685 if (isAllActivePredicate(DAG, Pg) && OpVT == MVT::nxv16i1)
27690 return getPTest(DAG, VT, Pg, Op, AArch64CC::ANY_ACTIVE);
27692 Op = DAG.getNode(ISD::XOR, DL, OpVT, Op, Pg);
27693 return getPTest(DAG, VT, Pg, Op, AArch64CC::NONE_ACTIVE);
27700 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Pg);
27704 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64, ID, Pg, Op);
27733 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
27734 SDValue Rdx = DAG.getNode(Opcode, DL, RdxVT, Pg, VecOp);
27783 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
27785 EVT CmpVT = Pg.getValueType();
27787 {Pg, Op1, Op2, Op.getOperand(2)});
27834 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
27838 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2);
27851 SDValue Pg = getPredicateForVector(DAG, DL, VT);
27863 Pg, Val, DAG.getUNDEF(ContainerVT));
27880 SDValue Pg = getPredicateForVector(DAG, DL, RoundVT);
27883 Val = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, RoundVT, Pg, Val,
27909 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
27918 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
27924 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
27927 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));
28041 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
28048 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
28053 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
28058 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));