Lines Matching defs:NewOp
13413 static SDValue tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
13424 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
13434 static SDValue tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
13470 Mov = DAG.getNode(NewOp, dl, MovTy,
13475 Mov = DAG.getNode(NewOp, dl, MovTy,
13487 static SDValue tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
13515 Mov = DAG.getNode(NewOp, dl, MovTy,
13520 Mov = DAG.getNode(NewOp, dl, MovTy,
13532 static SDValue tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op,
13552 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
13563 static SDValue tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
13574 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
13584 static SDValue tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
13605 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
13816 SDValue NewOp;
13818 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
13820 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
13822 return NewOp;
13824 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
13826 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
13828 return NewOp;
13879 SDValue NewOp;
13880 if ((NewOp =
13882 (NewOp =
13884 (NewOp =
13886 (NewOp =
13888 (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
13889 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
13890 return NewOp;
13893 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG,
13895 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG,
13897 (NewOp =
13899 return NewOp;
13921 if (SDValue NewOp = TryMOVIWithBits(NegBits)) {
13927 DAG.getNode(AArch64ISD::NVCAST, DL, VFVT, NewOp)));
15469 unsigned NewOp) const {
15471 return LowerToPredicatedOp(Op, DAG, NewOp);
18235 SDValue NewOp = DAG.getNode(N->getOpcode(), DL, HalfVT, NewN0, NewN1);
18238 DL, VT, NewOp);
19071 SDValue NewOp;
19082 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
19084 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
19086 return NewOp;
19089 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
19091 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
19093 return NewOp;
20707 SDValue NewOp = GenCombinedTree(Op0, Op1, DAG);
20726 NewOp, DAG.getConstant(0, DL, MVT::i64));
20728 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, Op0.getValueType(), NewOp,
20738 SDValue Ext = DAG.getNode(Other.getOpcode(), DL, DVT, NewOp);
22521 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
22522 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
27557 unsigned NewOp) const {
27586 if (isMergePassthruOpcode(NewOp))
27589 auto ScalableRes = DAG.getNode(NewOp, DL, ContainerVT, Operands);
27603 if (isMergePassthruOpcode(NewOp))
27606 return DAG.getNode(NewOp, DL, VT, Operands, Op->getFlags());