Lines Matching defs:N1
5071 SDValue N1 = N.getOperand(1);
5072 return N0->hasOneUse() && N1->hasOneUse() &&
5073 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5082 SDValue N1 = N.getOperand(1);
5083 return N0->hasOneUse() && N1->hasOneUse() &&
5084 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5215 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG,
5218 bool IsN1SExt = isSignExtended(N1, DAG);
5223 bool IsN1ZExt = isZeroExtended(N1, DAG);
5231 !isExtendedBUILD_VECTOR(N1, DAG, false)) {
5236 ZextOperand = N1.getOperand(0);
5243 N1 = NewSext;
5253 if (DAG.MaskedValueIsZero(IsN0ZExt ? N1 : N0, Mask))
5270 if (IsN0ZExt && isAddSubZExt(N1, DAG)) {
5271 std::swap(N0, N1);
5290 SDValue N1 = Op.getOperand(1);
5296 N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5297 isNullConstant(N1.getOperand(1))) {
5299 N1 = N1.getOperand(0);
5314 unsigned NewOpc = selectUmullSmull(N0, N1, DAG, DL, isMLA);
5331 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
7160 SDValue N1) const {
7164 unsigned IID = getIntrinsicID(N1.getNode());
7167 N1.getOpcode() == AArch64ISD::UMULL ||
7169 N1.getOpcode() == AArch64ISD::SMULL)
18222 SDValue N1 = N->getOperand(1).getOperand(0);
18234 SDValue NewN1 = DAG.getNode(N->getOperand(1).getOpcode(), DL, HalfVT, N1);
18263 SDValue N1 = N->getOperand(1);
18281 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper);
18282 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal);
18285 if (IsAddSubWith1(N1)) {
18291 if (!isa<ConstantSDNode>(N1))
18294 ConstantSDNode *C = cast<ConstantSDNode>(N1);
18335 auto Shl = [&](SDValue N0, unsigned N1) {
18339 if (N1 >= N0.getValueSizeInBits())
18341 SDValue RHS = DAG.getConstant(N1, DL, MVT::i64);
18344 auto Add = [&](SDValue N0, SDValue N1) {
18345 if (!N0.getNode() || !N1.getNode())
18347 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
18349 auto Sub = [&](SDValue N0, SDValue N1) {
18350 if (!N0.getNode() || !N1.getNode())
18352 return DAG.getNode(ISD::SUB, DL, VT, N0, N1);
18361 // Can the const C be decomposed into (1+2^M1)*(1+2^N1), eg:
18671 SDValue N1 = N->getOperand(1);
18672 if (N1.getOpcode() != ISD::AND)
18681 SDValue O1 = N1->getOperand(j);
18689 AddSibling = N1->getOperand(1 - j);
18694 SubSibling = N1->getOperand(1 - j);
18722 ISD::isConstantSplatVector(N1->getOperand(j).getNode(), Val2) &&
18725 N0->getOperand(1 - i), N1->getOperand(1 - j));
18728 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
18744 N0->getOperand(1 - i), N1->getOperand(1 - j));
19244 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
19264 if (isNullConstant(N1) && hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&
19309 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
19310 unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
19329 SDValue N10 = N1->getOperand(0);
19395 N->isOnlyUserOf(N1.getNode())) {
19401 SDValue N10 = N1->getOperand(0);
19403 isBitwiseVectorNegate(N10) && N1->isOnlyUserOf(N10.getNode())) {
19409 DAG.getNode(ISD::TRUNCATE, dl, N1.getValueType(),
19425 N1->hasOneUse()) {
19428 SDValue N10 = N1->getOperand(0);
19429 SDValue N11 = N1->getOperand(1);
19466 ((IsRSHRN(N1) &&
19467 N0.getConstantOperandVal(1) == N1.getConstantOperandVal(1)) ||
19468 N1.isUndef())) {
19470 SDValue Y = N1.isUndef() ? DAG.getUNDEF(X.getValueType())
19471 : N1.getOperand(0).getOperand(0);
19485 N1Opc == AArch64ISD::ZIP2 && N0.getOperand(0) == N1.getOperand(0) &&
19486 N0.getOperand(1) == N1.getOperand(1)) {
19497 if (N->getNumOperands() == 2 && N0 == N1 && VT.getVectorNumElements() == 2) {
19514 SDValue RHS = N1->getOperand(0);
20008 SDValue N1 = CSel.getOperand(1);
20012 if (!isNegatedInteger(N0) && !isNegatedInteger(N1))
20016 SDValue N1N = getNegatedInteger(N1, DAG);
20375 // On many AArch64 processors (Cortex A78, Neoverse N1/N2/V1, etc), ADD with