Lines Matching defs:N0
5070 SDValue N0 = N.getOperand(0);
5072 return N0->hasOneUse() && N1->hasOneUse() &&
5073 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5081 SDValue N0 = N.getOperand(0);
5083 return N0->hasOneUse() && N1->hasOneUse() &&
5084 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5215 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG,
5217 bool IsN0SExt = isSignExtended(N0, DAG);
5222 bool IsN0ZExt = isZeroExtended(N0, DAG);
5230 !isExtendedBUILD_VECTOR(N0, DAG, false) &&
5234 ZextOperand = N0.getOperand(0);
5239 DAG.getSExtOrTrunc(ZextOperand, DL, N0.getValueType());
5241 N0 = NewSext;
5250 EVT VT = N0.getValueType();
5253 if (DAG.MaskedValueIsZero(IsN0ZExt ? N1 : N0, Mask))
5262 if (IsN1SExt && isAddSubSExt(N0, DAG)) {
5266 if (IsN1ZExt && isAddSubZExt(N0, DAG)) {
5271 std::swap(N0, N1);
5289 SDValue N0 = Op.getOperand(0);
5294 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5295 isNullConstant(N0.getOperand(1)) &&
5298 N0 = N0.getOperand(0);
5300 VT = N0.getValueType();
5314 unsigned NewOpc = selectUmullSmull(N0, N1, DAG, DL, isMLA);
5333 Op0 = skipExtensionForVectorMULL(N0, DAG);
5344 SDValue N00 = skipExtensionForVectorMULL(N0.getOperand(0), DAG);
5345 SDValue N01 = skipExtensionForVectorMULL(N0.getOperand(1), DAG);
5349 DAG.getNode(N0.getOpcode(), DL, VT,
7159 bool AArch64TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,
7161 if (!N0.hasOneUse())
7170 return N0.getOpcode() != ISD::ADD;
14090 SDValue N0 = N->getOperand(0);
14094 Vector = N0.getNode();
14098 N0.getValueType().getVectorElementType())
14100 } else if (Vector != N0.getNode()) {
17991 SDValue N0 = N->getOperand(0);
17996 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETGE, CCVal, DAG, DL);
17997 SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, Pow2MinusOne);
18006 SDValue Negs = DAG.getNode(AArch64ISD::SUBS, DL, VTs, Zero, N0);
18007 SDValue AndPos = DAG.getNode(ISD::AND, DL, VT, N0, Pow2MinusOne);
18221 SDValue N0 = N->getOperand(0).getOperand(0);
18223 EVT InVT = N0.getValueType();
18233 SDValue NewN0 = DAG.getNode(N->getOperand(0).getOpcode(), DL, HalfVT, N0);
18262 SDValue N0 = N->getOperand(0);
18280 if (IsAddSubWith1(N0)) {
18286 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper);
18287 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal);
18299 if (IsSVECntIntrinsic(N0) ||
18300 (N0->getOpcode() == ISD::TRUNCATE &&
18301 (IsSVECntIntrinsic(N0->getOperand(0)))))
18310 // More aggressively, some multiplications N0 * C can be lowered to
18321 if (N0->hasOneUse() && (isSignExtended(N0, DAG) ||
18322 isZeroExtended(N0, DAG)))
18335 auto Shl = [&](SDValue N0, unsigned N1) {
18336 if (!N0.getNode())
18339 if (N1 >= N0.getValueSizeInBits())
18342 return DAG.getNode(ISD::SHL, DL, VT, N0, RHS);
18344 auto Add = [&](SDValue N0, SDValue N1) {
18345 if (!N0.getNode() || !N1.getNode())
18347 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
18349 auto Sub = [&](SDValue N0, SDValue N1) {
18350 if (!N0.getNode() || !N1.getNode())
18352 return DAG.getNode(ISD::SUB, DL, VT, N0, N1);
18355 if (!N0.getNode())
18430 return Shl(Add(Shl(N0, ShiftAmt), N0), TrailingZeroes);
18433 return Sub(Shl(N0, ShiftAmt), N0);
18436 return Sub(Shl(N0, ShiftAmt), Shl(N0, TrailingZeroes));
18446 SDValue MVal = Add(Shl(N0, ShiftM1), N0);
18456 SDValue MVal = Add(Shl(N0, CVM.getZExtValue()), N0);
18457 return Add(Shl(MVal, CVN.getZExtValue()), N0);
18467 SDValue MVal = Sub(N0, Shl(N0, CVM.getZExtValue()));
18468 return Sub(N0, Shl(MVal, CVN.getZExtValue()));
18480 return Sub(N0, Shl(N0, ShiftAmt));
18483 return Negate(Add(Shl(N0, ShiftAmt), N0));
18486 return Sub(Shl(N0, TrailingZeroes), Shl(N0, ShiftAmt));
18557 SDValue N0 = N->getOperand(0);
18558 if (Subtarget->isNeonAvailable() && ISD::isNormalLoad(N0.getNode()) &&
18559 N0.hasOneUse() &&
18561 !cast<LoadSDNode>(N0)->isVolatile()) {
18562 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
18667 SDValue N0 = N->getOperand(0);
18668 if (N0.getOpcode() != ISD::AND)
18680 SDValue O0 = N0->getOperand(i);
18688 SubSibling = N0->getOperand(1 - i);
18693 AddSibling = N0->getOperand(1 - i);
18721 if (ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) &&
18724 return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i),
18725 N0->getOperand(1 - i), N1->getOperand(1 - j));
18727 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
18743 return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i),
18744 N0->getOperand(1 - i), N1->getOperand(1 - j));
19179 SDValue N0 = N->getOperand(0);
19180 EVT VT = N0.getValueType();
19188 if (!isPredicateCCSettingOp(N0))
19194 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::FIRST_ACTIVE);
19209 SDValue N0 = N->getOperand(0);
19210 EVT OpVT = N0.getValueType();
19231 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE);
19244 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
19248 bool IsStrict = N0->isStrictFPOpcode();
19251 if (N0.getOpcode() == AArch64ISD::DUP)
19252 return VT.isInteger() ? DAG.getZExtOrTrunc(N0.getOperand(0), SDLoc(N), VT)
19253 : N0.getOperand(0);
19264 if (isNullConstant(N1) && hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&
19265 (!IsStrict || N0.hasOneUse())) {
19266 SDLoc DL(N0);
19267 SDValue N00 = N0->getOperand(IsStrict ? 1 : 0);
19268 SDValue N01 = N0->getOperand(IsStrict ? 2 : 1);
19286 return DAG.getNode(N0->getOpcode(), DL, VT, Extract1, Extract2);
19292 SDValue Ret = DAG.getNode(N0->getOpcode(), DL,
19294 {N0->getOperand(0), Extract1, Extract2});
19296 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Ret.getValue(1));
19309 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
19310 unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
19328 SDValue N00 = N0->getOperand(0);
19394 N1Opc == ISD::TRUNCATE && N->isOnlyUserOf(N0.getNode()) &&
19400 SDValue N00 = N0->getOperand(0);
19402 if (isBitwiseVectorNegate(N00) && N0->isOnlyUserOf(N00.getNode()) &&
19407 DAG.getNode(ISD::TRUNCATE, dl, N0.getValueType(),
19424 DAG.getTargetLoweringInfo().isBinOp(N0Opc) && N0->hasOneUse() &&
19426 SDValue N00 = N0->getOperand(0);
19427 SDValue N01 = N0->getOperand(1);
19465 if (N->getNumOperands() == 2 && IsRSHRN(N0) &&
19467 N0.getConstantOperandVal(1) == N1.getConstantOperandVal(1)) ||
19469 SDValue X = N0.getOperand(0).getOperand(0);
19477 DAG.getConstant(1ULL << (N0.getConstantOperandVal(1) - 1), dl, BVT));
19479 DAG.getNode(AArch64ISD::VLSHR, dl, BVT, Add, N0.getOperand(1));
19485 N1Opc == AArch64ISD::ZIP2 && N0.getOperand(0) == N1.getOperand(0) &&
19486 N0.getOperand(1) == N1.getOperand(1)) {
19487 SDValue E0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(0),
19488 DAG.getUNDEF(N0.getValueType()));
19489 SDValue E1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(1),
19490 DAG.getUNDEF(N0.getValueType()));
19497 if (N->getNumOperands() == 2 && N0 == N1 && VT.getVectorNumElements() == 2) {
19499 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
19527 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
20007 SDValue N0 = CSel.getOperand(0);
20012 if (!isNegatedInteger(N0) && !isNegatedInteger(N1))
20015 SDValue N0N = getNegatedInteger(N0, DAG);
20281 SDValue N0 = N->getOperand(0);
20282 if (VT.isFixedLengthVector() && VT.is64BitVector() && N0.hasOneUse() &&
20283 N0.getOpcode() == AArch64ISD::DUP) {
20284 SDValue Op = N0.getOperand(0);
20286 N0.getOperand(0).getValueType().getScalarType() == MVT::i64)
20288 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Op);
24206 SDValue N0 = N->getOperand(0);
24207 EVT CCVT = N0.getValueType();
24209 if (isAllActivePredicate(DAG, N0))
24212 if (isAllInactivePredicate(N0))
24247 EVT CmpVT = N0.getOperand(0).getValueType();
24248 if (N0.getOpcode() != ISD::SETCC ||
24263 N0.getOperand(0), N0.getOperand(1),
24264 cast<CondCodeSDNode>(N0.getOperand(2))->get());
24276 SDValue N0 = N->getOperand(0);
24279 if (N0.getOpcode() != ISD::SETCC)
24288 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
24294 EVT SrcVT = N0.getOperand(0).getValueType();
24322 SDLoc DL(N0);
24324 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
24326 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
24327 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
24968 SDValue N0 = N->getOperand(0);
24983 if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) &&
24984 N0.hasOneUse() && Subtarget->useSVEForFixedLengthVectors() &&
24987 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
24990 N0.getValueType(), LN0->getMemOperand());
24993 N0.getNode(),
24994 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad,
24995 DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)),