Lines Matching defs:IntermediateVT

28654     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
28657       Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
28663   assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!");
28674     IntermediateVT = NewVT;
28691     IntermediateVT = RegisterVT = MVT::v16i8;
28694     IntermediateVT = RegisterVT = MVT::v8i16;
28697     IntermediateVT = RegisterVT = MVT::v4i32;
28700     IntermediateVT = RegisterVT = MVT::v2i64;
28703     IntermediateVT = RegisterVT = MVT::v8f16;
28706     IntermediateVT = RegisterVT = MVT::v4f32;
28709     IntermediateVT = RegisterVT = MVT::v2f64;
28712     IntermediateVT = RegisterVT = MVT::v8bf16;