Lines Matching defs:FVal
4086 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4091 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
4111 SDValue FVal = Sel.getOperand(3);
4117 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
4127 std::swap(TVal, FVal);
4137 FVal = Other;
4141 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
4225 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4231 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
10328 SDValue FVal = DAG.getConstant(0, dl, VT);
10352 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
10379 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
10389 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
10415 SDValue FVal = DAG.getConstant(0, DL, OpVT);
10423 return DAG.getNode(AArch64ISD::CSEL, DL, OpVT, FVal, TVal, CCVal,
10429 SDValue FVal, const SDLoc &dl,
10456 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
10492 // If both the TVal and the FVal are constants, see if we can swap them in
10495 std::swap(TVal, FVal);
10499 std::swap(TVal, FVal);
10503 // If TVal is a NOT we want to swap TVal and FVal so that we can match
10506 std::swap(TVal, FVal);
10511 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
10514 std::swap(TVal, FVal);
10523 // If both TVal and FVal are constants, see if FVal is the
10561 // Swap TVal and FVal if necessary.
10563 std::swap(TVal, FVal);
10569 // Drop FVal since we can get its value by simply inverting/negating
10571 FVal = TVal;
10579 // FVal, respectively.
10589 FVal = LHS;
10598 FVal = DAG.getConstant(0, dl, FVal.getValueType());
10605 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
10625 ConstantFPSDNode *CFVal = dyn_cast<ConstantFPSDNode>(FVal);
10633 FVal.getValueType() == LHS.getValueType())
10634 FVal = LHS;
10640 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
10698 SDValue FVal = Op.getOperand(3);
10700 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
10707 SDValue FVal = Op->getOperand(2);
10713 FVal = DAG.getNode(ISD::BITCAST, DL, MVT::nxv16i1, FVal);
10715 DAG.getNode(ISD::SELECT, DL, MVT::nxv16i1, CCVal, TVal, FVal);
10722 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
10733 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
10748 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
10770 FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32,
10771 DAG.getUNDEF(MVT::f32), FVal);
10774 SDValue Res = LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
21071 SDValue FVal = DAG.getConstant(0, DL, OutVT);
21091 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);