Lines Matching defs:DCI
17928 TargetLowering::DAGCombinerInfo &DCI,
17930 if (DCI.isBeforeLegalizeOps())
18244 TargetLowering::DAGCombinerInfo &DCI,
18254 if (DCI.isBeforeLegalizeOps())
18582 TargetLowering::DAGCombinerInfo &DCI,
18650 static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
18653 SelectionDAG &DAG = DCI.DAG;
18828 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
18831 SelectionDAG &DAG = DCI.DAG;
18840 if (SDValue Res = tryCombineToBSL(N, DCI, TLI))
18885 TargetLowering::DAGCombinerInfo &DCI) {
18886 SelectionDAG &DAG = DCI.DAG;
18941 if (DCI.isBeforeLegalizeOps())
18998 TargetLowering::DAGCombinerInfo &DCI) {
19005 SelectionDAG &DAG = DCI.DAG;
19022 if (!DCI.isBeforeLegalize() &&
19037 TargetLowering::DAGCombinerInfo &DCI) {
19038 SelectionDAG &DAG = DCI.DAG;
19046 if (SDValue R = performANDSETCCCombine(N,DCI))
19053 return performSVEAndCombine(N, DCI);
19100 TargetLowering::DAGCombinerInfo &DCI) {
19101 SelectionDAG &DAG = DCI.DAG;
19172 TargetLowering::DAGCombinerInfo &DCI,
19176 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize())
19192 SelectionDAG &DAG = DCI.DAG;
19202 TargetLowering::DAGCombinerInfo &DCI,
19206 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize())
19229 SelectionDAG &DAG = DCI.DAG;
19235 performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
19238 if (SDValue Res = performFirstTrueTestVectorCombine(N, DCI, Subtarget))
19240 if (SDValue Res = performLastTrueTestVectorCombine(N, DCI, Subtarget))
19243 SelectionDAG &DAG = DCI.DAG;
19305 TargetLowering::DAGCombinerInfo &DCI,
19417 if (DCI.isBeforeLegalizeOps())
19473 X.getValueType().getDoubleNumVectorElementsVT(*DCI.DAG.getContext());
19532 performExtractSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
19534 if (DCI.isBeforeLegalizeOps())
19555 performInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
19597 TargetLowering::DAGCombinerInfo &DCI,
19601 if (DCI.isBeforeLegalizeOps())
20036 TargetLowering::DAGCombinerInfo &DCI) {
20037 SelectionDAG &DAG = DCI.DAG;
20038 if (DCI.isBeforeLegalizeOps())
20143 TargetLowering::DAGCombinerInfo &DCI,
20425 performSVEMulAddSubCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
20426 SelectionDAG &DAG = DCI.DAG;
20428 if (!DCI.isAfterLegalizeDAG())
20753 TargetLowering::DAGCombinerInfo &DCI) {
20755 if (SDValue Val = performAddUADDVCombine(N, DCI.DAG))
20757 if (SDValue Val = performAddDotCombine(N, DCI.DAG))
20759 if (SDValue Val = performAddCSelIntoCSinc(N, DCI.DAG))
20761 if (SDValue Val = performNegCSelCombine(N, DCI.DAG))
20763 if (SDValue Val = performVectorExtCombine(N, DCI.DAG))
20765 if (SDValue Val = performAddCombineForShiftedOperands(N, DCI.DAG))
20767 if (SDValue Val = performSubAddMULCombine(N, DCI.DAG))
20769 if (SDValue Val = performSVEMulAddSubCombine(N, DCI))
20771 if (SDValue Val = performAddSubIntoVectorOp(N, DCI.DAG))
20774 if (SDValue Val = performExtBinopLoadFold(N, DCI.DAG))
20777 return performAddSubLongCombine(N, DCI);
20788 TargetLowering::DAGCombinerInfo &DCI,
20790 if (DCI.isBeforeLegalizeOps())
20994 TargetLowering::DAGCombinerInfo &DCI,
20996 if (DCI.isBeforeLegalize())
21179 TargetLowering::DAGCombinerInfo &DCI,
21181 if (DCI.isBeforeLegalize())
21218 SelectionDAG &DAG = DCI.DAG;
21232 DCI.CombineTo(Lo, R.getValue(0));
21233 DCI.CombineTo(Hi, R.getValue(1));
21239 TargetLowering::DAGCombinerInfo &DCI,
21241 SelectionDAG &DAG = DCI.DAG;
21248 return tryCombineFixedPointConvert(N, DCI, DAG);
21283 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
21507 return tryConvertSVEWideCompare(N, ISD::SETEQ, DCI, DAG);
21509 return tryConvertSVEWideCompare(N, ISD::SETNE, DCI, DAG);
21511 return tryConvertSVEWideCompare(N, ISD::SETGE, DCI, DAG);
21513 return tryConvertSVEWideCompare(N, ISD::SETGT, DCI, DAG);
21515 return tryConvertSVEWideCompare(N, ISD::SETLT, DCI, DAG);
21517 return tryConvertSVEWideCompare(N, ISD::SETLE, DCI, DAG);
21519 return tryConvertSVEWideCompare(N, ISD::SETUGE, DCI, DAG);
21521 return tryConvertSVEWideCompare(N, ISD::SETUGT, DCI, DAG);
21523 return tryConvertSVEWideCompare(N, ISD::SETULT, DCI, DAG);
21525 return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG);
21536 return tryCombineWhileLo(N, DCI, Subtarget);
21548 performSignExtendSetCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
21588 TargetLowering::DAGCombinerInfo &DCI,
21594 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
21599 tryCombineLongOpWithDup(Intrinsic::not_intrinsic, ABDNode, DCI, DAG);
21609 return performSignExtendSetCCCombine(N, DCI, DAG);
21935 static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
22377 TargetLowering::DAGCombinerInfo &DCI) {
22391 if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm)
22401 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
22427 TargetLowering::DAGCombinerInfo &DCI,
22429 if (DCI.isBeforeLegalizeOps())
22432 SelectionDAG &DAG = DCI.DAG;
22531 DCI.CombineTo(LD, NewResults);
22532 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
22533 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
22543 TargetLowering::DAGCombinerInfo &DCI,
22547 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22548 !DCI.isBeforeLegalizeOps());
22551 DCI.CommitTargetLoweringOpt(TLO);
22638 TargetLowering::DAGCombinerInfo &DCI,
22642 performTBISimplification(N->getOperand(1), DCI, DAG);
22912 TargetLowering::DAGCombinerInfo &DCI,
22933 if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND &&
22942 if (SDValue Split = splitStores(N, DCI, DAG, Subtarget))
22946 performTBISimplification(N->getOperand(2), DCI, DAG))
22970 TargetLowering::DAGCombinerInfo &DCI,
23148 SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) {
23152 if (!DCI.isBeforeLegalize())
23186 TargetLowering::DAGCombinerInfo &DCI,
23188 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23313 DCI.CombineTo(N, NewResults);
23314 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
23552 TargetLowering::DAGCombinerInfo &DCI,
23631 TargetLowering::DAGCombinerInfo &DCI,
23640 if (SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3))
23687 DCI.CombineTo(N, BR, false);
23795 TargetLowering::DAGCombinerInfo &DCI,
23809 return performCONDCombine(N, DCI, DAG, 2, 3);
23861 performVecReduceBitwiseCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
23864 if (DCI.isBeforeLegalize() &&
23877 TargetLowering::DAGCombinerInfo &DCI,
23926 if (DCI.isBeforeLegalize() && VT.isScalarInteger() &&
23953 TargetLowering::DAGCombinerInfo &DCI,
23962 SDValue Res = DCI.DAG.getNode(GenericOpcode, DL, VT, N->ops());
23963 return DCI.DAG.getMergeValues({Res, DCI.DAG.getConstant(0, DL, MVT::i32)},
23968 if (SDNode *Generic = DCI.DAG.getNodeIfExists(
23969 GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS}))
23970 DCI.CombineTo(Generic, SDValue(N, 0));
24014 performSetccMergeZeroCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
24018 SelectionDAG &DAG = DCI.DAG;
24046 if (DCI.isAfterLegalizeDAG())
24134 TargetLowering::DAGCombinerInfo &DCI,
24274 TargetLowering::DAGCombinerInfo &DCI) {
24275 SelectionDAG &DAG = DCI.DAG;
24317 assert(DCI.isBeforeLegalize() ||
24339 TargetLowering::DAGCombinerInfo &DCI) {
24344 if (VT.is64BitVector() && DCI.isAfterLegalizeDAG()) {
24345 EVT LVT = VT.getDoubleNumVectorElementsVT(*DCI.DAG.getContext());
24347 if (SDNode *LN = DCI.DAG.getNodeIfExists(N->getOpcode(),
24348 DCI.DAG.getVTList(LVT), Ops)) {
24349 return DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SDValue(LN, 0),
24350 DCI.DAG.getConstant(0, DL, MVT::i64));
24355 if (DCI.isAfterLegalizeDAG()) {
24367 return DCI.DAG.getNode(Opcode, DL, VT, EXTRACT_VEC_ELT.getOperand(0),
24373 return performPostLD1Combine(N, DCI, false);
24722 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
24758 if (DCI.isBeforeLegalizeOps())
24844 DCI.CombineTo(N, ExtLoad);
24845 DCI.CombineTo(Src.getNode(), ExtLoad, ExtLoad.getValue(1));
24958 performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
24962 return performPostLD1Combine(N, DCI, true);
24966 TargetLowering::DAGCombinerInfo &DCI,
24983 if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) &&
24991 DCI.CombineTo(N, ExtLoad);
24992 DCI.CombineTo(
25060 TargetLowering::DAGCombinerInfo &DCI,
25062 if (DCI.isBeforeLegalizeOps())
25194 TargetLowering::DAGCombinerInfo &DCI,
25197 tryCombineLongOpWithDup(Intrinsic::not_intrinsic, N, DCI, DAG))
25200 if (SDValue Val = tryCombineMULLWithUZP1(N, DCI, DAG))
25207 performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
25219 if (DCI.isBeforeLegalizeOps())
25256 DAGCombinerInfo &DCI) const {
25257 SelectionDAG &DAG = DCI.DAG;
25265 return performVecReduceBitwiseCombine(N, DCI, DAG);
25268 return performAddSubCombine(N, DCI);
25270 return performBuildVectorCombine(N, DCI, DAG);
25274 return performFlagSettingCombine(N, DCI, ISD::AND);
25284 return performFlagSettingCombine(N, DCI, AArch64ISD::ADC);
25288 return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
25296 SDValue(N, 0), DemandedBits, DemandedElts, DCI))
25302 return performXorCombine(N, DAG, DCI, Subtarget);
25304 return performMulCombine(N, DAG, DCI, Subtarget);
25312 return performFpToIntCombine(N, DAG, DCI, Subtarget);
25314 return performORCombine(N, DCI, Subtarget, *this);
25316 return performANDCombine(N, DCI);
25318 return performFADDCombine(N, DCI);
25320 return performIntrinsicCombine(N, DCI, Subtarget);
25324 return performExtendCombine(N, DCI, DAG);
25326 return performSignExtendInRegCombine(N, DCI, DAG);
25328 return performConcatVectorsCombine(N, DCI, DAG);
25330 return performExtractSubvectorCombine(N, DCI, DAG);
25332 return performInsertSubvectorCombine(N, DCI, DAG);
25334 return performSelectCombine(N, DCI);
25336 return performVSelectCombine(N, DCI.DAG);
25338 return performSETCCCombine(N, DCI, DAG);
25340 return performLOADCombine(N, DCI, DAG, Subtarget);
25342 return performSTORECombine(N, DCI, DAG, Subtarget);
25344 return performMSTORECombine(N, DCI, DAG, Subtarget);
25347 return performMaskedGatherScatterCombine(N, DCI, DAG);
25349 return performFPExtendCombine(N, DAG, DCI, Subtarget);
25351 return performBRCONDCombine(N, DCI, DAG);
25354 return performTBZCombine(N, DCI, DAG);
25356 return performCSELCombine(N, DCI, DAG);
25362 return performDUPCombine(N, DCI);
25376 return performSetccMergeZeroCombine(N, DCI);
25396 return performVectorShiftCombine(N, *this, DCI);
25402 return performInsertVectorEltCombine(N, DCI);
25404 return performExtractVectorEltCombine(N, DCI, Subtarget);
25406 return performVecReduceAddCombine(N, DCI.DAG, Subtarget);
25412 return performMULLCombine(N, DCI, DAG);
25454 return performNEONPostLDSTCombine(N, DCI, DAG);
25598 return performScalarToVectorCombine(N, DCI, DAG);