Lines Matching defs:CSEL
2323 case AArch64ISD::CSEL: {
2554 MAKE_CASE(AArch64ISD::CSEL)
4091 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
4141 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
4171 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);
4181 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);
4231 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
6592 // Generate SUBS and CSEL for integer abs.
6602 // Generate SUBS & CSEL.
6606 return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,
10352 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
10360 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
10379 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
10383 // this case, we emit the first CSEL and then emit a second using the output
10389 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
10392 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
10423 return DAG.getNode(AArch64ISD::CSEL, DL, OpVT, FVal, TVal, CCVal,
10490 unsigned Opcode = AArch64ISD::CSEL;
10504 // with a CSINV rather than a CSEL.
10512 // that we can match with a CSNEG rather than a CSEL.
10525 // instead of a CSEL in that case.
10568 if (Opcode != AArch64ISD::CSEL) {
10577 // is one, zero or negative one in the case of a CSEL. We can always
10578 // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
10581 if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
10638 // Emit first, and possibly only, CSEL.
10640 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
10642 // If we need a second CSEL, emit it, using the output of the first as the
10646 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
10649 // Otherwise, return the output of the first CSEL.
10748 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
18765 if (CSel0.getOpcode() != AArch64ISD::CSEL ||
18766 CSel1.getOpcode() != AArch64ISD::CSEL)
18823 return DAG.getNode(AArch64ISD::CSEL, DL, VT, CSel0.getOperand(0),
19757 if (Op.getOpcode() != AArch64ISD::CSEL)
19843 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
19884 /// CSEL(c, 1, cc) + b => CSINC(b+c, b, cc)
19895 if (LHS.getOpcode() != AArch64ISD::CSEL &&
19898 if (LHS.getOpcode() != AArch64ISD::CSEL &&
19910 // The CSEL should include a const one operand, and the CSNEG should include
19917 if (!(LHS.getOpcode() == AArch64ISD::CSEL &&
19923 // Switch CSEL(1, c, cc) to CSEL(c, 1, !cc)
19924 if (LHS.getOpcode() == AArch64ISD::CSEL && CTVal->isOne() &&
19947 assert(((LHS.getOpcode() == AArch64ISD::CSEL && CFVal->isOne()) ||
20004 if (CSel.getOpcode() != AArch64ISD::CSEL || !CSel->hasOneUse())
20020 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0N, N1N, CSel.getOperand(2),
20082 // (CSEL 1 0 CC Cond) => CC
20083 // (CSEL 0 1 CC Cond) => !CC
20085 if (Op.getOpcode() != AArch64ISD::CSEL)
21089 // NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
21091 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);
23733 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) x)) => (CSEL l r cc2 cond)
23734 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) y)) => (CSEL l r !cc2 cond)
23737 // (CSEL l r NE (CMP (CSEL x y cc2 cond) x)) => (CSEL l r !cc2 cond)
23738 // (CSEL l r NE (CMP (CSEL x y cc2 cond) y)) => (CSEL l r cc2 cond)
23753 if (CmpRHS.getOpcode() == AArch64ISD::CSEL)
23755 else if (CmpLHS.getOpcode() != AArch64ISD::CSEL)
23790 return DAG.getNode(AArch64ISD::CSEL, DL, VT, L, R, CCValue, Cond);
23793 // Optimize CSEL instructions
23797 // CSEL x, x, cc -> x
23804 // CSEL 0, cttz(X), eq(X, 0) -> AND cttz bitwidth-1
23805 // CSEL cttz(X), 0, ne(X, 0) -> AND cttz bitwidth-1
23891 LHS->getOpcode() == AArch64ISD::CSEL &&
23894 // Invert CSEL's condition.
23900 SDValue CSEL =
23901 DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),
23904 return DAG.getZExtOrTrunc(CSEL, DL, VT);
25355 case AArch64ISD::CSEL: