Lines Matching defs:NumVecs
365 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
375 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
377 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
379 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
380 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
381 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
384 void SelectContiguousMultiVectorLoad(SDNode *N, unsigned NumVecs,
387 void SelectDestructiveMultiIntrinsic(SDNode *N, unsigned NumVecs,
392 void SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, unsigned Opcode);
393 void SelectClamp(SDNode *N, unsigned NumVecs, unsigned Opcode);
396 void SelectFrintFromVT(SDNode *N, unsigned NumVecs, unsigned Opcode);
399 void SelectMultiVectorMove(SDNode *N, unsigned NumVecs, unsigned BaseReg,
401 void SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
423 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
424 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
425 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
426 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
427 void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
1466 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
1476 N->op_begin() + Vec0Off + NumVecs);
1483 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1678 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
1691 for (unsigned i = 0; i < NumVecs; ++i)
1695 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1707 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1723 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1727 if (NumVecs == 1)
1730 for (unsigned i = 0; i < NumVecs; ++i)
1735 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1861 void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs,
1864 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1869 for (unsigned i = 0; i < NumVecs; ++i)
1877 unsigned NumVecs,
1889 N->op_begin() + StartIdx + NumVecs);
1897 Zm = GetMultiVecOperand(NumVecs + FirstVecIdx);
1899 Zm = N->getOperand(NumVecs + FirstVecIdx);
1908 for (unsigned i = 0; i < NumVecs; ++i)
1915 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs,
1938 for (unsigned i = 0; i < NumVecs; ++i)
1943 unsigned ChainIdx = NumVecs;
1949 unsigned NumVecs,
1973 for (unsigned i = 0; i < NumVecs; ++i)
1978 unsigned ChainIdx = NumVecs;
1983 void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs,
1987 SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
2018 void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs,
2023 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
2025 SDValue Zn = N->getOperand(1 + NumVecs);
2026 SDValue Zm = N->getOperand(2 + NumVecs);
2032 for (unsigned i = 0; i < NumVecs; ++i)
2067 void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs,
2091 for (unsigned I = 0; I < NumVecs; ++I)
2096 unsigned ChainIdx = NumVecs;
2101 void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
2127 for (unsigned I = 0; I < NumVecs; ++I)
2133 unsigned ChainIdx = NumVecs;
2168 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
2175 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
2178 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
2188 void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
2194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
2201 N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),
2204 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
2230 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
2239 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
2243 N->getOperand(NumVecs + 1), // base register
2244 N->getOperand(NumVecs + 2), // Incremental
2286 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
2293 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
2303 unsigned LaneNo = N->getConstantOperandVal(NumVecs + 2);
2306 N->getOperand(NumVecs + 3), N->getOperand(0)};
2313 for (unsigned i = 0; i < NumVecs; ++i) {
2320 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
2324 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
2331 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
2342 unsigned LaneNo = N->getConstantOperandVal(NumVecs + 1);
2347 N->getOperand(NumVecs + 2), // Base register
2348 N->getOperand(NumVecs + 3), // Incremental
2353 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
2357 if (NumVecs == 1) {
2364 for (unsigned i = 0; i < NumVecs; ++i) {
2374 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
2378 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
2385 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
2393 unsigned LaneNo = N->getConstantOperandVal(NumVecs + 2);
2396 N->getOperand(NumVecs + 3), N->getOperand(0)};
2406 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
2413 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
2424 unsigned LaneNo = N->getConstantOperandVal(NumVecs + 1);
2427 N->getOperand(NumVecs + 2), // Base Register
2428 N->getOperand(NumVecs + 3), // Incremental