Lines Matching defs:RegInfo

349   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
350   if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF))
482   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
494       RegInfo->hasStackRealignment(MF))
1095   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1119   if (!RegInfo->hasStackRealignment(*MF) && !TLI->hasInlineStackProbe(*MF))
1147   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1174   if (RegInfo->hasStackRealignment(MF))
1237   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1246     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1247     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
1267                 .addImm(RegInfo->getSEHRegNum(Reg0))
1268                 .addImm(RegInfo->getSEHRegNum(Reg1))
1277     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1288     unsigned Reg =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1297     unsigned Reg0 =  RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
1298     unsigned Reg1 =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1316                 .addImm(RegInfo->getSEHRegNum(Reg0))
1317                 .addImm(RegInfo->getSEHRegNum(Reg1))
1324     int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
1333     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
1342     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
1343     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1355     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
1356     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
1730   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
2023       NumBytes && !IsFunclet && RegInfo->hasStackRealignment(MF);
2207   if (!IsFunclet && RegInfo->hasBasePointer(MF)) {
2208     TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
2244           *RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,
2448       const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
2449       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
2575     const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
2576     unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
2690   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(
2693   return RegInfo->getLocalAddressRegister(MF) == AArch64::FP
2713   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(
2742     } else if (isCSR && RegInfo->hasStackRealignment(MF)) {
2748     } else if (hasFP(MF) && !RegInfo->hasStackRealignment(MF)) {
2760         bool CanUseBP = RegInfo->hasBasePointer(MF);
2773       } else if (MF.hasEHFunclets() && !RegInfo->hasBasePointer(MF)) {
2791       ((isFixed || isCSR) || !RegInfo->hasStackRealignment(MF) || !UseFP) &&
2805                       RegInfo->hasStackRealignment(MF))) {
2806       FrameReg = RegInfo->getFrameRegister(MF);
2810     FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()
2822     FrameReg = RegInfo->getFrameRegister(MF);
2827   if (RegInfo->hasBasePointer(MF))
2828     FrameReg = RegInfo->getBaseRegister();
3631   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
3641   unsigned BasePointerReg = RegInfo->hasBasePointer(MF)
3642                                 ? RegInfo->getBaseRegister()
3683           !RegInfo->isReservedReg(MF, Reg)) {
3697           !RegInfo->isReservedReg(MF, PairedReg))
3759       dbgs() << ' ' << printReg(Reg, RegInfo);
3785   if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
3796       LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
3854     MachineFunction &MF, const TargetRegisterInfo *RegInfo,
3915     const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
3933     unsigned Size = RegInfo->getSpillSize(*RC);
3934     Align Alignment(RegInfo->getSpillAlign(*RC));
4965       const AArch64RegisterInfo &RegInfo =
4967       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);