Lines Matching defs:RPI
2983 RegPairInfo RPI;
2984 RPI.Reg1 = CSI[i].getReg();
2986 if (AArch64::GPR64RegClass.contains(RPI.Reg1))
2987 RPI.Type = RegPairInfo::GPR;
2988 else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
2989 RPI.Type = RegPairInfo::FPR64;
2990 else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
2991 RPI.Type = RegPairInfo::FPR128;
2992 else if (AArch64::ZPRRegClass.contains(RPI.Reg1))
2993 RPI.Type = RegPairInfo::ZPR;
2994 else if (AArch64::PPRRegClass.contains(RPI.Reg1))
2995 RPI.Type = RegPairInfo::PPR;
2996 else if (RPI.Reg1 == AArch64::VG)
2997 RPI.Type = RegPairInfo::VG;
3004 AArch64InstrInfo::isFpOrNEON(RPI.Reg1))
3006 LastReg = RPI.Reg1;
3012 switch (RPI.Type) {
3015 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
3018 RPI.Reg2 = NextReg;
3022 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI,
3024 RPI.Reg2 = NextReg;
3028 RPI.Reg2 = NextReg;
3034 if (((RPI.Reg1 - AArch64::Z0) & 1) == 0 && (NextReg == RPI.Reg1 + 1))
3035 RPI.Reg2 = NextReg;
3048 assert((!RPI.isPaired() ||
3052 assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP ||
3053 RPI.Reg1 == AArch64::LR) &&
3057 assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg1 != AArch64::FP ||
3058 RPI.Reg2 == AArch64::LR) &&
3066 (RPI.isPaired() &&
3067 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
3068 RPI.Reg1 + 1 == RPI.Reg2))) &&
3071 RPI.FrameIdx = CSI[i].getFrameIdx();
3073 RPI.isPaired()) // RPI.FrameIdx must be the lower index of the pair
3074 RPI.FrameIdx = CSI[i + RegInc].getFrameIdx();
3075 int Scale = RPI.getScale();
3077 int OffsetPre = RPI.isScalable() ? ScalableByteOffset : ByteOffset;
3080 if (RPI.isScalable())
3081 ScalableByteOffset += StackFillDir * (RPI.isPaired() ? 2 * Scale : Scale);
3083 ByteOffset += StackFillDir * (RPI.isPaired() ? 2 * Scale : Scale);
3088 ((!IsWindows && RPI.Reg2 == AArch64::FP) ||
3089 (IsWindows && RPI.Reg2 == AArch64::LR)))
3094 if (NeedGapToAlignStack && !NeedsWinCFI && !RPI.isScalable() &&
3095 RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired() &&
3098 assert(MFI.getObjectAlign(RPI.FrameIdx) <= Align(16));
3102 MFI.setObjectAlignment(RPI.FrameIdx, Align(16));
3106 int OffsetPost = RPI.isScalable() ? ScalableByteOffset : ByteOffset;
3115 ((!IsWindows && RPI.Reg2 == AArch64::FP) ||
3116 (IsWindows && RPI.Reg2 == AArch64::LR)))
3118 RPI.Offset = Offset / Scale;
3120 assert((!RPI.isPaired() ||
3121 (!RPI.isScalable() && RPI.Offset >= -64 && RPI.Offset <= 63) ||
3122 (RPI.isScalable() && RPI.Offset >= -256 && RPI.Offset <= 255)) &&
3128 ((!IsWindows && RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
3129 (IsWindows && RPI.Reg1 == AArch64::FP && RPI.Reg2 == AArch64::LR)))
3132 RegPairs.push_back(RPI);
3133 if (RPI.isPaired())
3171 for (auto &RPI : RegPairs) {
3172 MIB.addReg(RPI.Reg1);
3173 MIB.addReg(RPI.Reg2);
3176 if (!MRI.isReserved(RPI.Reg1))
3177 MBB.addLiveIn(RPI.Reg1);
3178 if (RPI.isPaired() && !MRI.isReserved(RPI.Reg2))
3179 MBB.addLiveIn(RPI.Reg2);
3184 for (const RegPairInfo &RPI : llvm::reverse(RegPairs)) {
3185 unsigned Reg1 = RPI.Reg1;
3186 unsigned Reg2 = RPI.Reg2;
3201 switch (RPI.Type) {
3203 StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
3208 StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
3213 StrOpc = RPI.isPaired() ? AArch64::STPQi : AArch64::STRQui;
3218 StrOpc = RPI.isPaired() ? AArch64::ST1B_2Z_IMM : AArch64::STR_ZXI;
3254 AFI->setStreamingVGIdx(RPI.FrameIdx);
3260 AFI->setVGIdx(RPI.FrameIdx);
3287 AFI->setVGIdx(RPI.FrameIdx);
3292 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
3293 dbgs() << ") -> fi#(" << RPI.FrameIdx;
3294 if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1;
3302 unsigned FrameIdxReg1 = RPI.FrameIdx;
3303 unsigned FrameIdxReg2 = RPI.FrameIdx + 1;
3304 if (NeedsWinCFI && RPI.isPaired()) {
3309 if (RPI.isPaired() && RPI.isScalable()) {
3338 MIB.addReg(/*PairRegs*/ AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0));
3344 .addImm(RPI.Offset) // [sp, #offset*scale],
3356 if (RPI.isPaired()) {
3366 .addImm(RPI.Offset) // [sp, #offset*scale],
3377 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
3379 if (RPI.isPaired())
3409 for (auto &RPI : RegPairs) {
3410 MIB.addReg(RPI.Reg1, RegState::Define);
3411 MIB.addReg(RPI.Reg2, RegState::Define);
3427 for (const RegPairInfo &RPI : RegPairs) {
3428 unsigned Reg1 = RPI.Reg1;
3429 unsigned Reg2 = RPI.Reg2;
3442 switch (RPI.Type) {
3444 LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
3449 LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
3454 LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
3459 LdrOpc = RPI.isPaired() ? AArch64::LD1B_2Z_IMM : AArch64::LDR_ZXI;
3472 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
3473 dbgs() << ") -> fi#(" << RPI.FrameIdx;
3474 if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1;
3480 unsigned FrameIdxReg1 = RPI.FrameIdx;
3481 unsigned FrameIdxReg2 = RPI.FrameIdx + 1;
3482 if (NeedsWinCFI && RPI.isPaired()) {
3488 if (RPI.isPaired() && RPI.isScalable()) {
3504 MIB.addReg(/*PairRegs*/ AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0),
3511 .addImm(RPI.Offset) // [sp, #offset*scale]
3521 if (RPI.isPaired()) {
3529 .addImm(RPI.Offset) // [sp, #offset*scale]