Lines Matching defs:CSI
598 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
599 if (CSI.empty())
607 for (const auto &Info : CSI) {
638 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
639 if (CSI.empty())
648 for (const auto &Info : CSI) {
710 const std::vector<CalleeSavedInfo> &CSI =
712 for (const auto &Info : CSI) {
727 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
728 if (CSI.empty())
736 for (const auto &Info : CSI) {
2944 MachineFunction &MF, ArrayRef<CalleeSavedInfo> CSI,
2948 if (CSI.empty())
2956 unsigned Count = CSI.size();
2972 // As the CSI array is reversed to match PrologEpilogInserter, iterate
2984 RPI.Reg1 = CSI[i].getReg();
3010 Register NextReg = CSI[i + RegInc].getReg();
3042 // GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
3049 (CSI[i].getFrameIdx() + RegInc == CSI[i + RegInc].getFrameIdx())) &&
3071 RPI.FrameIdx = CSI[i].getFrameIdx();
3074 RPI.FrameIdx = CSI[i + RegInc].getFrameIdx();
3141 // CSI, which goes top down), to create the gap above it.
3143 MFI.setObjectAlignment(CSI[0].getFrameIdx(), Align(16));
3152 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
3160 computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs, hasFP(MF));
3395 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
3405 computeCalleeSaveRegisterPairs(MF, CSI, TRI, RegPairs, hasFP(MF));
3855 std::vector<CalleeSavedInfo> &CSI, unsigned &MinCSFrameIndex,
3862 // the top, thus have the CSI array start from the highest registers.)
3864 std::reverse(CSI.begin(), CSI.end());
3866 if (CSI.empty())
3900 for (unsigned I = 0; I < CSI.size(); I++)
3901 if (CSI[I].getReg() == AArch64::LR) {
3903 CSI.insert(CSI.begin() + I, VGSaves.begin(), VGSaves.end());
3908 CSI.insert(CSI.end(), VGSaves.begin(), VGSaves.end());
3913 for (auto &CS : CSI) {
3997 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
3998 for (auto &CS : CSI) {