Lines Matching defs:UseAdd

204   unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
207   unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
210   unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
213   unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
217   unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1080         ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1084         ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1165 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1192   if (UseAdd && isa<Constant>(LHS) && !isa<Constant>(RHS))
1196   if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1201   if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1220       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1223       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1227       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1238     return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1257       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1280           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1296   return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1299 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1318   unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1336 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1360   unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1381 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1404   unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1423 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1445   unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1496   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
1535   return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1564   return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1570   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1578   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
3727         emitAddSub_rx(/*UseAdd=*/false, MVT::i64, MulReg, MulSubReg,
4942     ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,