Lines Matching defs:SrcVT
199 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
234 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
259 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
262 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
265 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1188 MVT SrcVT = RetVT;
1214 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1294 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
2835 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2836 if (SrcVT == MVT::f128 || SrcVT == MVT::f16 || SrcVT == MVT::bf16)
2840 if (SrcVT == MVT::f64) {
2874 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2877 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2879 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2885 if (SrcVT == MVT::i64) {
3045 MVT SrcVT = ArgVT;
3046 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
3055 MVT SrcVT = ArgVT;
3056 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3961 MVT SrcVT = SrcEVT.getSimpleVT();
3964 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3965 SrcVT != MVT::i8)
3981 if (SrcVT == MVT::i64) {
4105 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4107 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4109 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4110 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4118 unsigned SrcBits = SrcVT.getSizeInBits();
4124 if (RetVT == SrcVT) {
4131 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4171 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4208 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4210 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4212 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4213 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4221 unsigned SrcBits = SrcVT.getSizeInBits();
4227 if (RetVT == SrcVT) {
4234 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4272 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4275 SrcVT = RetVT;
4276 SrcBits = SrcVT.getSizeInBits();
4287 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4324 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4326 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4328 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4329 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4337 unsigned SrcBits = SrcVT.getSizeInBits();
4343 if (RetVT == SrcVT) {
4350 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4392 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4404 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4408 // FastISel does not have plumbing to deal with extensions where the SrcVT or
4410 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4414 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
4415 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
4421 switch (SrcVT.SimpleTy) {
4514 MVT SrcVT) {
4542 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4571 MVT SrcVT;
4575 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
4579 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4590 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4605 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4672 MVT SrcVT = VT;
4678 SrcVT = VT;
4687 SrcVT = VT;
4699 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
4735 MVT SrcVT = RetVT;
4742 SrcVT = TmpVT;
4751 SrcVT = TmpVT;
4765 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4768 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4771 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4811 MVT RetVT, SrcVT;
4813 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
4819 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4821 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4823 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4825 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)