Lines Matching defs:SetFlags
205 const Value *RHS, bool SetFlags = false,
208 unsigned RHSReg, bool SetFlags = false,
211 uint64_t Imm, bool SetFlags = false,
215 uint64_t ShiftImm, bool SetFlags = false,
219 uint64_t ShiftImm, bool SetFlags = false,
237 bool SetFlags = false, bool WantResult = true,
241 bool SetFlags = false, bool WantResult = true,
1166 const Value *RHS, bool SetFlags,
1220 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1223 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1227 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1239 SetFlags, WantResult);
1258 ShiftVal, SetFlags, WantResult);
1281 ShiftVal, SetFlags, WantResult);
1296 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1300 unsigned RHSReg, bool SetFlags,
1318 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1337 uint64_t Imm, bool SetFlags,
1360 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1362 if (SetFlags)
1384 uint64_t ShiftImm, bool SetFlags,
1404 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1426 uint64_t ShiftImm, bool SetFlags,
1445 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1447 if (SetFlags)
1491 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1497 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1534 bool SetFlags, bool WantResult, bool IsZExt) {
1535 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1563 bool SetFlags, bool WantResult, bool IsZExt) {
1564 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1571 /*SetFlags=*/true, WantResult);
1579 ShiftImm, /*SetFlags=*/true, WantResult);
3697 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3701 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3705 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3709 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3728 AArch64_AM::SXTW, /*ShiftImm=*/0, /*SetFlags=*/true,