Lines Matching defs:RetVT
199 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
204 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
207 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
213 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
217 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
226 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
227 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
236 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
240 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
243 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
245 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
248 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
250 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
254 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
255 unsigned emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1);
256 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
257 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
258 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
259 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
261 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
262 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
264 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
265 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1165 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1170 switch (RetVT.SimpleTy) {
1188 MVT SrcVT = RetVT;
1189 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1214 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1220 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1223 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1227 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1238 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1257 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1280 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1294 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1296 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1299 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1308 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1317 bool Is64Bit = RetVT == MVT::i64;
1336 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1341 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1359 bool Is64Bit = RetVT == MVT::i64;
1381 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1390 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1394 if (ShiftImm >= RetVT.getSizeInBits())
1403 bool Is64Bit = RetVT == MVT::i64;
1423 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1432 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1444 bool Is64Bit = RetVT == MVT::i64;
1489 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1491 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1495 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {
1496 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
1500 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1501 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1516 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1526 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1533 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1535 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1562 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1564 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1568 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1570 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1574 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1578 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1582 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1606 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1627 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1641 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1651 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1653 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1654 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1660 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1672 switch (RetVT.SimpleTy) {
1698 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1699 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1705 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1717 if (ShiftImm >= RetVT.getSizeInBits())
1722 switch (RetVT.SimpleTy) {
1740 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1741 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,
1749 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);
1752 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1828 bool IsRet64Bit = RetVT == MVT::i64;
1877 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
1975 MVT RetVT = VT;
1979 if (isTypeSupported(ZE->getType(), RetVT))
1982 RetVT = VT;
1984 if (isTypeSupported(SE->getType(), RetVT))
1987 RetVT = VT;
1993 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
2016 if (RetVT == MVT::i64 && VT <= MVT::i32) {
3363 MVT RetVT;
3367 if (!isTypeLegal(RetTy, RetVT))
3370 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3544 MVT RetVT;
3545 if (!isTypeLegal(II->getType(), RetVT))
3548 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3557 bool Is64Bit = RetVT == MVT::f64;
4047 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4049 switch (RetVT.SimpleTy) {
4054 RetVT = MVT::i32;
4061 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4065 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4066 if (RetVT != MVT::i64)
4073 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4074 if (RetVT != MVT::i64)
4081 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
4086 switch (RetVT.SimpleTy) {
4095 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4105 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4107 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4112 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4113 RetVT == MVT::i64) && "Unexpected return value type.");
4115 bool Is64Bit = (RetVT == MVT::i64);
4117 unsigned DstBits = RetVT.getSizeInBits();
4124 if (RetVT == SrcVT) {
4131 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4171 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4183 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
4188 switch (RetVT.SimpleTy) {
4197 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4208 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4210 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4215 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4216 RetVT == MVT::i64) && "Unexpected return value type.");
4218 bool Is64Bit = (RetVT == MVT::i64);
4220 unsigned DstBits = RetVT.getSizeInBits();
4227 if (RetVT == SrcVT) {
4234 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4267 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4272 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4275 SrcVT = RetVT;
4287 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4299 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
4304 switch (RetVT.SimpleTy) {
4313 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4315 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false);
4324 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4326 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4331 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4332 RetVT == MVT::i64) && "Unexpected return value type.");
4334 bool Is64Bit = (RetVT == MVT::i64);
4336 unsigned DstBits = RetVT.getSizeInBits();
4343 if (RetVT == SrcVT) {
4350 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4383 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4392 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4513 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4542 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4570 MVT RetVT;
4572 if (!isTypeSupported(I->getType(), RetVT))
4579 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4590 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4605 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4725 MVT RetVT;
4726 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4729 if (RetVT.isVector())
4735 MVT SrcVT = RetVT;
4765 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4768 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4771 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4793 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4796 ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4799 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4811 MVT RetVT, SrcVT;
4815 if (!isTypeLegal(I->getType(), RetVT))
4819 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4821 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4823 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4825 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4831 switch (RetVT.SimpleTy) {
4851 MVT RetVT;
4852 if (!isTypeLegal(I->getType(), RetVT))
4856 switch (RetVT.SimpleTy) {