Lines Matching defs:ResultReg
362 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
364 ResultReg)
368 return ResultReg;
385 Register ResultReg = createResultReg(RC);
387 ResultReg).addReg(ZeroReg, getKillRegState(true));
388 return ResultReg;
421 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
423 TII.get(TargetOpcode::COPY), ResultReg)
426 return ResultReg;
439 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
440 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
443 return ResultReg;
463 unsigned ResultReg;
473 ResultReg = createResultReg(&AArch64::GPR32RegClass);
476 ResultReg = createResultReg(&AArch64::GPR64RegClass);
480 ResultReg)
485 return ResultReg;
494 .addReg(ResultReg, RegState::Kill)
527 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
529 ResultReg)
535 return ResultReg;
1065 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
1067 ResultReg)
1072 Addr.setReg(ResultReg);
1076 unsigned ResultReg = 0;
1080 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1084 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1089 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1092 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1095 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
1098 if (!ResultReg)
1101 Addr.setReg(ResultReg);
1110 unsigned ResultReg;
1113 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), Offset);
1115 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1117 if (!ResultReg)
1119 Addr.setReg(ResultReg);
1216 unsigned ResultReg = 0;
1220 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1223 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1227 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1229 if (ResultReg)
1230 return ResultReg;
1257 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1259 if (ResultReg)
1260 return ResultReg;
1280 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1282 if (ResultReg)
1283 return ResultReg;
1321 unsigned ResultReg;
1323 ResultReg = createResultReg(RC);
1325 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1330 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1333 return ResultReg;
1366 unsigned ResultReg;
1368 ResultReg = createResultReg(RC);
1370 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1374 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1378 return ResultReg;
1407 unsigned ResultReg;
1409 ResultReg = createResultReg(RC);
1411 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1416 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1420 return ResultReg;
1451 unsigned ResultReg;
1453 ResultReg = createResultReg(RC);
1455 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1460 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1464 return ResultReg;
1545 unsigned ResultReg;
1547 ResultReg = emitAddSub_ri(false, VT, Op0, -Imm);
1549 ResultReg = emitAddSub_ri(true, VT, Op0, Imm);
1551 if (ResultReg)
1552 return ResultReg;
1558 ResultReg = emitAddSub_rr(true, VT, Op0, CReg);
1559 return ResultReg;
1603 unsigned ResultReg = 0;
1606 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1608 if (ResultReg)
1609 return ResultReg;
1627 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1628 if (ResultReg)
1629 return ResultReg;
1641 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1642 if (ResultReg)
1643 return ResultReg;
1652 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1655 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1657 return ResultReg;
1695 Register ResultReg =
1700 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1702 return ResultReg;
1737 Register ResultReg =
1742 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1744 return ResultReg;
1863 Register ResultReg = createResultReg(RC);
1865 TII.get(Opc), ResultReg);
1870 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1);
1872 ResultReg = ANDReg;
1882 .addReg(ResultReg, getKillRegState(true))
1884 ResultReg = Reg64;
1886 return ResultReg;
1897 unsigned ResultReg;
1902 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1905 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1908 if (!ResultReg)
1911 updateValueMap(I, ResultReg);
1923 unsigned ResultReg;
1928 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1931 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1934 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1937 if (!ResultReg)
1940 updateValueMap(I, ResultReg);
1992 unsigned ResultReg =
1994 if (!ResultReg)
2020 ResultReg = std::prev(I)->getOperand(0).getReg();
2023 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
2026 updateValueMap(I, ResultReg);
2047 updateValueMap(IntExtVal, ResultReg);
2051 updateValueMap(I, ResultReg);
2544 unsigned ResultReg = 0;
2549 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2551 TII.get(TargetOpcode::COPY), ResultReg)
2555 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2559 if (ResultReg) {
2560 updateValueMap(I, ResultReg);
2568 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2596 ResultReg)
2601 updateValueMap(I, ResultReg);
2610 ResultReg)
2615 updateValueMap(I, ResultReg);
2667 Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2669 updateValueMap(SI, ResultReg);
2788 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC);
2789 updateValueMap(I, ResultReg);
2802 Register ResultReg = createResultReg(&AArch64::FPR64RegClass);
2804 ResultReg).addReg(Op);
2805 updateValueMap(I, ResultReg);
2818 Register ResultReg = createResultReg(&AArch64::FPR32RegClass);
2820 ResultReg).addReg(Op);
2821 updateValueMap(I, ResultReg);
2851 Register ResultReg = createResultReg(
2853 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
2855 updateValueMap(I, ResultReg);
2897 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
2898 updateValueMap(I, ResultReg);
3005 Register ResultReg = createResultReg(RC);
3007 TII.get(TargetOpcode::COPY), ResultReg)
3009 updateValueMap(&Arg, ResultReg);
3117 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy);
3121 unsigned CopyReg = ResultReg + i;
3134 CLI.ResultReg = ResultReg;
3331 unsigned ResultReg = emitLoad(VT, VT, Src);
3332 if (!ResultReg)
3335 if (!emitStore(VT, ResultReg, Dest))
3475 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
3477 TII.get(AArch64::ADDXri), ResultReg)
3482 updateValueMap(II, ResultReg);
3592 updateValueMap(II, CLI.ResultReg);
3614 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
3615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
3617 updateValueMap(II, ResultReg);
3640 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
3641 if (!ResultReg)
3644 updateValueMap(II, ResultReg);
3836 Register ResultReg =
3838 updateValueMap(II, ResultReg);
3980 unsigned ResultReg;
4001 ResultReg = emitAnd_ri(MVT::i32, Reg32, Mask);
4002 assert(ResultReg && "Unexpected AND instruction emission failure.");
4004 ResultReg = createResultReg(&AArch64::GPR32RegClass);
4006 TII.get(TargetOpcode::COPY), ResultReg)
4010 updateValueMap(I, ResultReg);
4023 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1);
4024 assert(ResultReg && "Unexpected AND instruction emission failure.");
4032 .addReg(ResultReg)
4034 ResultReg = Reg64;
4036 return ResultReg;
4099 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4101 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4102 return ResultReg;
4125 Register ResultReg = createResultReg(RC);
4127 TII.get(TargetOpcode::COPY), ResultReg)
4129 return ResultReg;
4202 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4204 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4205 return ResultReg;
4228 Register ResultReg = createResultReg(RC);
4230 TII.get(TargetOpcode::COPY), ResultReg)
4232 return ResultReg;
4318 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4320 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4321 return ResultReg;
4344 Register ResultReg = createResultReg(RC);
4346 TII.get(TargetOpcode::COPY), ResultReg)
4348 return ResultReg;
4591 Register ResultReg = createResultReg(&AArch64::GPR64RegClass);
4593 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4597 SrcReg = ResultReg;
4605 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4606 if (!ResultReg)
4609 updateValueMap(I, ResultReg);
4649 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg);
4650 updateValueMap(I, ResultReg);
4698 unsigned ResultReg =
4701 if (ResultReg) {
4702 updateValueMap(I, ResultReg);
4715 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg);
4717 if (!ResultReg)
4720 updateValueMap(I, ResultReg);
4733 unsigned ResultReg = 0;
4765 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4768 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4771 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4774 if (!ResultReg)
4777 updateValueMap(I, ResultReg);
4789 unsigned ResultReg = 0;
4793 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4796 ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4799 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4803 if (!ResultReg)
4806 updateValueMap(I, ResultReg);
4842 Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg);
4843 if (!ResultReg)
4846 updateValueMap(I, ResultReg);
4884 updateValueMap(I, CLI.ResultReg);
4907 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2);
4908 if (!ResultReg)
4910 updateValueMap(I, ResultReg);
4940 unsigned ResultReg;
4942 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,
4945 ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2);
4947 if (!ResultReg)
4950 updateValueMap(I, ResultReg);