Lines Matching defs:Op0Reg

258   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
259   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
261   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
262   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
264   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
265   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
3636     Register Op0Reg = getRegForValue(II->getOperand(0));
3637     if (!Op0Reg)
3640     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
4081 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
4099   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4183 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
4199     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Mask);
4202   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4299 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
4315     Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false);
4318   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4758     Register Op0Reg = getRegForValue(Op0);
4759     if (!Op0Reg)
4765       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4768       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4771       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4781   Register Op0Reg = getRegForValue(I->getOperand(0));
4782   if (!Op0Reg)
4793     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4796     ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4799     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4838   Register Op0Reg = getRegForValue(I->getOperand(0));
4839   if (!Op0Reg)
4842   Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg);