Lines Matching defs:LHSReg

207   unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
210   unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
213   unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
217   unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
226   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
243   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
245   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
250   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
254   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
1209   Register LHSReg = getRegForValue(LHS);
1210   if (!LHSReg)
1214     LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1220       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1223       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1227       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1238     return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1257       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1280           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1296   return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1299 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1302   assert(LHSReg && RHSReg && "Invalid register number.");
1304   if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
1328   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1331       .addReg(LHSReg)
1336 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1339   assert(LHSReg && "Invalid register number.");
1373   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1375       .addReg(LHSReg)
1381 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1386   assert(LHSReg && RHSReg && "Invalid register number.");
1387   assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&
1414   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1417       .addReg(LHSReg)
1423 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1428   assert(LHSReg && RHSReg && "Invalid register number.");
1429   assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&
1458   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1461       .addReg(LHSReg)
1495 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {
1496   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
1511   Register LHSReg = getRegForValue(LHS);
1512   if (!LHSReg)
1518         .addReg(LHSReg);
1528       .addReg(LHSReg)
1568 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1570   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1574 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1578   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1599   Register LHSReg = getRegForValue(LHS);
1600   if (!LHSReg)
1606     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1627       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1641         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1652   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1661                                            unsigned LHSReg, uint64_t Imm) {
1696       fastEmitInst_ri(Opc, RC, LHSReg,
1706                                            unsigned LHSReg, unsigned RHSReg,
1738       fastEmitInst_rri(Opc, RC, LHSReg, RHSReg,
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,
1749   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);
3714       Register LHSReg = getRegForValue(LHS);
3715       if (!LHSReg)
3723         MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);
3733         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3735         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3736         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
3744       Register LHSReg = getRegForValue(LHS);
3745       if (!LHSReg)
3753         MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);
3762         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3764         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3765         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
3831     Register LHSReg = getRegForValue(II->getArgOperand(0));
3833     if (!LHSReg || !RHSReg)
3837         fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg);