Lines Matching defs:DestVT

234   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
235   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2827   MVT DestVT;
2828   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2842       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2844       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2847       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2849       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2852       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2860   MVT DestVT;
2861   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2864   if (DestVT == MVT::f16 || DestVT == MVT::bf16)
2867   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2887       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2889       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2892       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2894       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2897   Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
3044       MVT DestVT = VA.getLocVT();
3046       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
3054       MVT DestVT = VA.getLocVT();
3056       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3914     MVT DestVT = VA.getValVT();
3916     if (RVVT != DestVT) {
3924       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3962   MVT DestVT = DestEVT.getSimpleVT();
3967   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3968       DestVT != MVT::i1)
3983     switch (DestVT.SimpleTy) {
4014 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4015   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4016           DestVT == MVT::i64) &&
4019   if (DestVT == MVT::i8 || DestVT == MVT::i16)
4020     DestVT = MVT::i32;
4025     if (DestVT == MVT::i64) {
4038     if (DestVT == MVT::i64) {
4404 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4406   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4409   // DestVT are odd things, so test to make sure that they are both types we can
4410   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4412   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4413        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4425     return emiti1Ext(SrcReg, DestVT, IsZExt);
4427     if (DestVT == MVT::i64)
4434     if (DestVT == MVT::i64)
4441     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4448   if (DestVT == MVT::i8 || DestVT == MVT::i16)
4449     DestVT = MVT::i32;
4450   else if (DestVT == MVT::i64) {
4461       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4618   MVT DestVT = DestEVT.getSimpleVT();
4619   if (DestVT != MVT::i64 && DestVT != MVT::i32)
4623   bool Is64bit = (DestVT == MVT::i64);
4644       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;