Lines Matching +full:cs +full:- +full:extra +full:- +full:delay
1 //===--------------------- InstrBuilder.cpp ---------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "llvm-mca-instrbuilder"
61 // This map stores the number of cycles contributed by sub-resources that are
72 const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);
73 if (!PRE->ReleaseAtCycle) {
84 uint64_t Mask = ProcResourceMasks[PRE->ProcResourceIdx];
93 CycleSegment RCy(0, PRE->ReleaseAtCycle, false);
97 SuperResources[Super] += PRE->ReleaseAtCycle;
149 B.second.CS.subtract(A.second.size() - SuperResources[A.first]);
169 // On top of those 2cy, SchedWriteRes explicitly specifies an extra latency
171 // extra delay on top of the 2 cycles latency.
172 // During those extra cycles, HWPort01 is not usable by other instructions.
185 // Identify extra buffers that are consumed through super resources.
189 if (PR.BufferSize == -1)
210 uint64_t Current = BufferIDs & (-BufferIDs);
246 --NumExplicitDefs;
256 const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1);
280 // either the last operand of the sequence (excluding extra operands
284 // These assumptions work quite well for most out-of-order in-tree targets
290 // The algorithm allows non-register operands between register operand
292 // implicit operand increment (-mtriple=armv7):
312 // non-register operands between register definitions. The optional
313 // definition is still at index #(NumOperands-1).
315 // According to assumption 2. register reads start at #(NumExplicitDefs-1).
324 unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
326 // Iterate over the operands list, and skip non-register or constant register
330 unsigned OptionalDefIdx = MCDesc.getNumOperands() - 1;
446 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs();
450 --NumExplicitUses;
451 unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
547 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
573 bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant();
599 ID->NumMicroOps = SCDesc.NumMicroOps;
600 ID->SchedClassID = SchedClassID;
626 LLVM_DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
627 LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
635 if ((ID->IsRecyclable = !IsVariadic && !IsVariant)) {
693 NewIS->reset();
706 NewIS->setMayLoad(MCDesc.mayLoad());
707 NewIS->setMayStore(MCDesc.mayStore());
708 NewIS->setHasSideEffects(MCDesc.hasUnmodeledSideEffects());
709 NewIS->setBeginGroup(SCDesc.BeginGroup);
710 NewIS->setEndGroup(SCDesc.EndGroup);
711 NewIS->setRetireOOO(SCDesc.RetireOOO);
720 IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);
722 IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);
723 if (MCIA->isOptimizableRegisterMove(MCI, ProcID))
724 NewIS->setOptimizableMove();
734 // Skip non-register operands.
749 if (IsInstRecycled && Idx < NewIS->getUses().size()) {
750 NewIS->getUses()[Idx] = ReadState(RD, RegID);
751 RS = &NewIS->getUses()[Idx++];
753 NewIS->getUses().emplace_back(RD, RegID);
754 RS = &NewIS->getUses().back();
763 RS->setIndependentFromDef();
773 RS->setIndependentFromDef();
778 if (IsInstRecycled && Idx < NewIS->getUses().size())
779 NewIS->getUses().pop_back_n(NewIS->getUses().size() - Idx);
790 // underlying super-registers using an APInt.
794 // register writes implicitly clear the upper portion of a super-register.
796 MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);
812 if (IsInstRecycled && Idx < NewIS->getDefs().size()) {
813 NewIS->getDefs()[Idx++] =
818 NewIS->getDefs().emplace_back(WD, RegID,
825 if (IsInstRecycled && Idx < NewIS->getDefs().size())
826 NewIS->getDefs().pop_back_n(NewIS->getDefs().size() - Idx);