Lines Matching defs:MCI

239 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) {
243   for (I = 0, E = MCI.getNumOperands(); NumExplicitDefs && I < E; ++I) {
244     const MCOperand &Op = MCI.getOperand(I);
251         "Expected more register operand definitions.", MCI);
256     const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1);
257     if (I == MCI.getNumOperands() || !Op.isReg()) {
261       return make_error<InstructionError<MCInst>>(Message, MCI);
268 void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
270   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
324   unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
332   for (; i < MCI.getNumOperands() && CurrentDef < NumExplicitDefs; ++i) {
333     const MCOperand &Op = MCI.getOperand(i);
420     const MCOperand &Op = MCI.getOperand(OpIndex);
443 void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
445   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
451   unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
457     const MCOperand &Op = MCI.getOperand(OpIndex);
492     const MCOperand &Op = MCI.getOperand(OpIndex);
517 hash_code hashMCInst(const MCInst &MCI) {
518   hash_code InstructionHash = hash_combine(MCI.getOpcode(), MCI.getFlags());
519   for (unsigned I = 0; I < MCI.getNumOperands(); ++I) {
521         hash_combine(InstructionHash, hashMCOperand(MCI.getOperand(I)));
527                                     const MCInst &MCI) const {
540   return make_error<InstructionError<MCInst>>(std::string(Message), MCI);
543 Expected<unsigned> InstrBuilder::getVariantSchedClassID(const MCInst &MCI,
549         STI.resolveVariantSchedClass(SchedClassID, &MCI, &MCII, CPUID);
553         "unable to resolve scheduling class for write variant.", MCI);
560 InstrBuilder::createInstrDescImpl(const MCInst &MCI,
566   unsigned short Opcode = MCI.getOpcode();
572   unsigned SchedClassID = IM.getSchedClassID(MCII, MCI, IVec);
578         getVariantSchedClassID(MCI, SchedClassID);
590         "found an unsupported instruction in the input assembly sequence", MCI);
620   if (Error Err = verifyOperands(MCDesc, MCI))
623   populateWrites(*ID, MCI, SchedClassID);
624   populateReads(*ID, MCI, SchedClassID);
630   if (Error Err = verifyInstrDesc(*ID, MCI))
636     auto DKey = std::make_pair(MCI.getOpcode(), SchedClassID);
641   auto VDKey = std::make_pair(hashMCInst(MCI), SchedClassID);
650 InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI,
653   unsigned SchedClassID = IM.getSchedClassID(MCII, MCI, IVec);
655   auto DKey = std::make_pair(MCI.getOpcode(), SchedClassID);
660       getVariantSchedClassID(MCI, SchedClassID);
667   auto VDKey = std::make_pair(hashMCInst(MCI), SchedClassID);
671   return createInstrDescImpl(MCI, IVec);
677 InstrBuilder::createInstruction(const MCInst &MCI,
679   Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(MCI, IVec);
698     CreatedIS = std::make_unique<Instruction>(D, MCI.getOpcode());
702   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
720     IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);
722         IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);
723     if (MCIA->isOptimizableRegisterMove(MCI, ProcID))
733       const MCOperand &Op = MCI.getOperand(RD.OpIndex);
796     MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);
803                                  : MCI.getOperand(WD.OpIndex).getReg();