Lines Matching defs:WR
126 WriteRef &WR = RegisterMappings[RegID].first;
127 if (WR.getWriteState() == &WS)
128 WR.notifyExecuted(CurrentCycle);
364 WriteRef &WR = RegisterMappings[RegID].first;
365 if (WR.getWriteState() == &WS)
366 WR.commit();
497 unsigned RegisterFile::getElapsedCyclesFromWriteBack(const WriteRef &WR) const {
498 assert(WR.hasKnownWriteBackCycle() && "Write hasn't been committed yet!");
499 return CurrentCycle - WR.getWriteBackCycle();
519 const WriteRef &WR = RegisterMappings[RegID].first;
520 if (WR.getWriteState()) {
521 Writes.push_back(WR);
522 } else if (WR.hasKnownWriteBackCycle()) {
523 unsigned WriteResID = WR.getWriteResourceID();
526 unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
528 CommittedWrites.push_back(WR);
534 const WriteRef &WR = RegisterMappings[I].first;
535 if (WR.getWriteState()) {
536 Writes.push_back(WR);
537 } else if (WR.hasKnownWriteBackCycle()) {
538 unsigned WriteResID = WR.getWriteResourceID();
541 unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
543 CommittedWrites.push_back(WR);
558 for (const WriteRef &WR : Writes) {
559 const WriteState &WS = *WR.getWriteState();
562 << WR.getSourceIndex() << ")\n";
579 for (const WriteRef &WR : Writes) {
580 const WriteState *WS = WR.getWriteState();
588 Hazard.RegisterID = WR.getRegisterID();
596 Hazard.RegisterID = WR.getRegisterID();
603 for (const WriteRef &WR : CommittedWrites) {
604 unsigned WriteResID = WR.getWriteResourceID();
606 int Elapsed = static_cast<int>(getElapsedCyclesFromWriteBack(WR));
610 Hazard.RegisterID = WR.getRegisterID();
640 for (WriteRef &WR : DependentWrites) {
641 unsigned WriteResID = WR.getWriteResourceID();
642 WriteState &WS = *WR.getWriteState();
644 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance);
647 for (WriteRef &WR : CompletedWrites) {
648 unsigned WriteResID = WR.getWriteResourceID();
649 assert(WR.hasKnownWriteBackCycle() && "Invalid write!");
653 unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
655 RS.writeStartEvent(WR.getSourceIndex(), WR.getRegisterID(),