Lines Matching +full:num +full:- +full:vectors
1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
69 "jump-is-expensive", cl::init(false),
74 ("min-jump-table-entries", cl::init(4), cl::Hidden,
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
83 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
87 /// Minimum jump table density for -Os or -Oz functions.
89 "optsize-jump-table-density", cl::init(40), cl::Hidden,
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98 cl::desc("Don't mutate strict-float node to a legalize node"),
101 /// GetFPLibCall - Helper to return the right libcall for the given floating
118 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
153 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
196 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
245 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
294 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
340 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
736 // Carry-using overflow operations default to expand.
775 // Constrained floating-point operations default to expand.
910 unsigned EltWidth = RetTy->getScalarSizeInBits();
918 // If the command-line option was specified, ignore this request.
949 // First promote to a power-of-two size, then expand if necessary.
954 // Avoid multi-step promotion.
969 // Vectors with only one element are always scalarized.
975 // <3 x i8> -> <4 x i8> -> <4 x i32>
977 // Vectors with a number of elements that is not a power of two are always
978 // widened, for example <3 x i8> -> <4 x i8>.
989 // <4 x i140> -> <2 x i140>
1003 // Increase the bitwidth of the element to the next pow-of-two
1008 // Stop trying when getting a non-simple element type.
1048 // Widen odd vectors to next power of two.
1057 // Vectors with illegal element types are expanded.
1073 // Scalable vectors cannot be scalarized, so splitting or widening is
1077 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1079 // FIXME: We don't support non-power-of-2-sized vectors for now.
1091 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1099 if (!TLI->isTypeLegal(NewVT))
1108 MVT DestVT = TLI->getRegisterType(NewVT);
1110 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1118 /// isLegalRC - Return true if the value types that can be represented by the
1128 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1134 MachineFunction &MF = *MI->getMF();
1138 // PATCHPOINT MetaArgs - live-in, read only, direct
1139 // STATEPOINT Deopt Spill - live-through, read only, indirect
1140 // STATEPOINT Deopt Alloca - live-through, read only, direct
1143 // STATEPOINT GC Spill - live-through, read/write, indirect
1144 // STATEPOINT GC Alloca - live-through, read/write, direct
1145 // The live-in vs live-through is handled already (the live through ones are
1149 if (llvm::none_of(MI->operands(),
1153 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1158 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1159 MachineOperand &MO = MI->getOperand(i);
1167 TiedTo = MI->findTiedOperandIdx(i);
1170 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1175 // with the canonical set of five x86 addressing-mode operands.
1180 // indirect-mem-ref tag, size, #FI, offset.
1184 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1190 // direct-mem-ref tag, #FI, offset.
1197 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1200 assert(MFI.getObjectOffset(FI) != -1);
1204 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1209 MIB->addMemOperand(MF, MMO);
1212 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1213 MI->eraseFromParent();
1217 /// findRepresentativeClass - Return the largest legal super-reg register class
1221 // isTypeLegal over as well - a massive change that would just require
1230 // Compute the set of all super-register classes.
1231 BitVector SuperRegRC(TRI->getNumRegClasses());
1238 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1240 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1249 /// computeRegisterProperties - Once all of the register classes are added,
1263 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1270 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1272 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1280 for (unsigned IntReg = LargestIntReg - 1;
1281 IntReg >= (unsigned)MVT::i1; --IntReg) {
1393 // Try to promote the elements of integer vectors. If no legal
1394 // promotion was found, fall through to the widen-vector method.
1398 // Promote vectors of integers to vectors with the same number
1487 // not a sub-register class / subreg register class) legal register class for
1501 assert(!VT.isVector() && "No default SetCC type for vectors!");
1509 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1526 // This handles things like <2 x float> -> <4 x float> and
1527 // <4 x i1> -> <4 x i32>.
1545 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1569 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1577 // end with a scalar if the target doesn't support vectors.
1594 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1618 SI->getParent()->getParent()->hasOptSize() ||
1619 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1657 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);
1660 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1662 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1679 else if (i == NumParts - 1 && i != 0)
1688 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1706 // Assume that an access that meets the ABI-specified alignment is fast.
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1755 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1756 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1835 // compiler-rt provides a variable with a magic name. Targets that do not
1836 // link with compiler-rt may also provide such a variable.
1837 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1840 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1842 Type *StackPtrTy = PointerType::getUnqual(M->getContext());
1849 // We use the initial-exec TLS model because we do not support the
1856 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1858 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1860 (UseTLS ? "" : "not ") + "be thread-local");
1872 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1873 auto *PtrTy = PointerType::getUnqual(M->getContext());
1875 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);
1879 //===----------------------------------------------------------------------===//
1881 //===----------------------------------------------------------------------===//
1883 /// isLegalAddressingMode - Return true if the addressing mode represented
1895 // Allows a sign-extended 16-bit immediate field.
1896 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1924 //===----------------------------------------------------------------------===//
1926 //===----------------------------------------------------------------------===//
1932 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1936 G->setVisibility(GlobalValue::HiddenVisibility);
1957 GV->setDSOLocal(true);
2006 //===----------------------------------------------------------------------===//
2008 //===----------------------------------------------------------------------===//
2014 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2018 /// This string should match the corresponding option to the front-end's
2019 /// "-mrecip" flag assuming those strings have been passed through in an
2020 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2022 std::string Name = VT.isVector() ? "vec-" : "";
2056 Value = RefStepChar - '0';
2060 report_fatal_error("Invalid refinement step for -recip.");
2195 // Single-element vectors are scalarized, so we should generally avoid having
2268 if (RMW->isVolatile())
2271 if (CmpX->isVolatile())
2284 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2299 //===----------------------------------------------------------------------===//
2301 //===----------------------------------------------------------------------===//
2329 // Constants-like instructions should be close to their users.
2330 // We don't want long live-ranges for them.
2337 unsigned RematCost = TTI->getGISelRematGlobalCost();