Lines Matching defs:WideVT

6404     EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), Size * 2);
6406       WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
6408     if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
6409       X = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, X);
6410       Y = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, Y);
6411       Y = DAG.getNode(ISD::MUL, dl, WideVT, X, Y);
6412       Y = DAG.getNode(ISD::SRL, dl, WideVT, Y,
6413                       DAG.getShiftAmountConstant(EltBits, WideVT, dl));
6587     EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), Size * 2);
6589       WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
6591     if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
6592       X = DAG.getNode(ISD::ZERO_EXTEND, dl, WideVT, X);
6593       Y = DAG.getNode(ISD::ZERO_EXTEND, dl, WideVT, Y);
6594       Y = DAG.getNode(ISD::MUL, dl, WideVT, X, Y);
6595       Y = DAG.getNode(ISD::SRL, dl, WideVT, Y,
6596                       DAG.getShiftAmountConstant(EltBits, WideVT, dl));
10516                                         bool Signed, EVT WideVT,
10525   if (WideVT == MVT::i16)
10527   else if (WideVT == MVT::i32)
10529   else if (WideVT == MVT::i64)
10531   else if (WideVT == MVT::i128)
10581       // Halves of WideVT are packed into registers in different order
10586       Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first;
10589       Ret = makeLibCall(DAG, LC, WideVT, Args, CallOptions, dl).first;
10627   EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
10628   forceExpandWideMUL(DAG, dl, Signed, WideVT, LHS, HiLHS, RHS, HiRHS, Lo, Hi);
10695   EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
10703   } else if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
10706     SDValue LHSExt = DAG.getNode(Ext, dl, WideVT, LHS);
10707     SDValue RHSExt = DAG.getNode(Ext, dl, WideVT, RHS);
10708     SDValue Res = DAG.getNode(ISD::MUL, dl, WideVT, LHSExt, RHSExt);
10711         DAG.getNode(ISD::SRA, dl, WideVT, Res,
10712                     DAG.getShiftAmountConstant(VTSize, WideVT, dl));
10983   EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
10985     WideVT =
10986         EVT::getVectorVT(*DAG.getContext(), WideVT, VT.getVectorElementCount());
11000   } else if (isTypeLegal(WideVT)) {
11001     LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
11002     RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
11003     SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
11006         DAG.getShiftAmountConstant(VT.getScalarSizeInBits(), WideVT, dl);
11008                           DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt));