Lines Matching defs:SRA
959 assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
960 "SRL or SRA node is required here!");
1025 case ISD::SRA: {
2020 case ISD::SRA: {
2118 SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1);
3618 case ISD::SRA:
4903 N0.getOpcode() == ISD::SRA && isa<ConstantSDNode>(N0.getOperand(1)) &&
6148 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
6270 SDValue SRA =
6271 DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, VT));
6276 return SRA;
6278 Created.push_back(SRA.getNode());
6279 return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
6432 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
8135 // ISD::SRA/L nodes haven't. Insert an AND to be safe, it's usually optimized
8139 SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8149 Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8209 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
9237 (!isOperationLegalOrCustom(ISD::SRA, VT) ||
9245 ISD::SRA, dl, VT, Op,
9310 unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL;
10435 SDValue Shift = DAG.getNode(ISD::SRA, dl, VT, SumDiff,
10499 DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS);
10614 // The high part is obtained by SRA'ing all but one of the bits of low
10618 ISD::SRA, dl, VT, LHS,
10621 ISD::SRA, dl, VT, RHS,
10711 DAG.getNode(ISD::SRA, dl, WideVT, Res,
10757 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo,
10829 RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS,
10976 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
11020 SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);