Lines Matching defs:N0
752 SDValue N0 = Op.getOperand(0);
753 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts,
755 return N0;
3229 SDValue N0 = Op.getOperand(0);
3230 if (TLO.DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts,
3232 return TLO.CombineTo(Op, N0);
3236 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1)
3239 TLO.DAG.getFreeze(N0.getOperand(0))));
3818 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
3823 std::swap(N0, N1);
3831 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask);
3976 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3979 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
3980 std::swap(N0, N1);
3983 EVT OpVT = N0.getValueType();
3984 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
3995 if (DAG.MaskedValueIsZero(N0, UpperBits))
3996 return DAG.getBoolExtOrTrunc(N0, DL, VT, OpVT);
4006 auto *AndC = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4008 isTypeLegal(OpVT) && N0.hasOneUse()) {
4012 SDValue Trunc = DAG.getZExtOrTrunc(N0.getOperand(0), DL, NarrowVT);
4023 if (N0.getOperand(0) == N1) {
4024 X = N0.getOperand(1);
4025 Y = N0.getOperand(0);
4026 } else if (N0.getOperand(1) == N1) {
4027 X = N0.getOperand(0);
4028 Y = N0.getOperand(1);
4046 isCondCodeLegal(Cond, N0.getSimpleValueType()))
4047 return DAG.getSetCC(DL, VT, N0, Zero, Cond);
4048 } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
4062 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
4080 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
4087 // N0 should be: add %x, (1 << (KeptBits-1))
4088 if (N0->getOpcode() != ISD::ADD)
4093 if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
4096 SDValue X = N0->getOperand(0);
4164 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
4209 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
4212 X = N0.getOperand(0);
4213 SDValue Mask = N0.getOperand(1);
4233 /// the 1st operand (N0). Callers are expected to swap the N0/N1 parameters to
4235 SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
4238 unsigned BOpcode = N0.getOpcode();
4247 EVT OpVT = N0.getValueType();
4248 SDValue X = N0.getOperand(0);
4249 SDValue Y = N0.getOperand(1);
4262 if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
4274 SDValue N0, const APInt &C1,
4279 SDValue CTPOP = N0;
4280 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && !VT.isVector() &&
4281 N0.getScalarValueSizeInBits() > Log2_32(N0.getOperand(0).getScalarValueSizeInBits()))
4282 CTPOP = N0.getOperand(0);
4347 static SDValue foldSetCCWithRotate(EVT VT, SDValue N0, SDValue N1,
4366 if (SDValue R = getRotateSource(N0))
4375 EVT OpVT = N0.getValueType();
4376 if (N0.hasOneUse() && N0.getOpcode() == ISD::OR && C1->isZero()) {
4377 if (SDValue R = getRotateSource(N0.getOperand(0))) {
4378 SDValue NewOr = DAG.getNode(ISD::OR, dl, OpVT, R, N0.getOperand(1));
4381 if (SDValue R = getRotateSource(N0.getOperand(1))) {
4382 SDValue NewOr = DAG.getNode(ISD::OR, dl, OpVT, R, N0.getOperand(0));
4390 static SDValue foldSetCCWithFunnelShift(EVT VT, SDValue N0, SDValue N1,
4402 if (!N0.hasOneUse() ||
4403 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR))
4406 unsigned BitWidth = N0.getScalarValueSizeInBits();
4407 auto *ShAmtC = isConstOrConstSplat(N0.getOperand(2));
4413 if (N0.getOpcode() == ISD::FSHR)
4434 EVT OpVT = N0.getValueType();
4435 EVT ShAmtVT = N0.getOperand(2).getValueType();
4436 SDValue F0 = N0.getOperand(0);
4437 SDValue F1 = N0.getOperand(1);
4458 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
4464 EVT OpVT = N0.getValueType();
4468 if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
4472 isConstOrConstSplat(N0, /*AllowUndefs*/ false, /*AllowTruncate*/ true);
4483 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
4484 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
4492 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
4493 DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) &&
4494 !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1}))
4495 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
4497 if (SDValue V = foldSetCCWithRotate(VT, N0, N1, Cond, dl, DAG))
4500 if (SDValue V = foldSetCCWithFunnelShift(VT, N0, N1, Cond, dl, DAG))
4507 if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG))
4517 N0.getOpcode() == ISD::MUL && N0.hasOneUse() &&
4518 (N0->getFlags().hasNoUnsignedWrap() ||
4519 N0->getFlags().hasNoSignedWrap()) &&
4521 SDValue IsXZero = DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
4522 SDValue IsYZero = DAG.getSetCC(dl, VT, N0.getOperand(1), N1, Cond);
4530 if (N0.getOpcode() == ISD::SRL && (C1.isZero() || C1.isOne()) &&
4531 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
4532 llvm::has_single_bit<uint32_t>(N0.getScalarValueSizeInBits())) {
4533 if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) {
4535 ShAmt->getAPIntValue() == Log2_32(N0.getScalarValueSizeInBits())) {
4545 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
4546 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero,
4560 DCI.isBeforeLegalize() && N0->hasOneUse()) {
4561 unsigned MinBits = N0.getValueSizeInBits();
4564 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
4566 MinBits = N0->getOperand(0).getValueSizeInBits();
4567 PreExt = N0->getOperand(0);
4568 } else if (N0->getOpcode() == ISD::AND) {
4570 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
4573 PreExt = N0->getOperand(0);
4575 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
4577 MinBits = N0->getOperand(0).getValueSizeInBits();
4578 PreExt = N0->getOperand(0);
4580 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
4584 PreExt = N0;
4588 PreExt = N0;
4619 SDValue TopSetCC = N0->getOperand(0);
4620 unsigned N0Opc = N0->getOpcode();
4626 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
4649 N0.getOpcode() == ISD::AND && C1 == 0 &&
4650 N0.getNode()->hasOneUse() &&
4651 isa<LoadSDNode>(N0.getOperand(0)) &&
4652 N0.getOperand(0).getNode()->hasOneUse() &&
4653 isa<ConstantSDNode>(N0.getOperand(1))) {
4654 auto *Lod = cast<LoadSDNode>(N0.getOperand(0));
4661 unsigned origWidth = N0.getValueSizeInBits();
4667 const APInt &Mask = N0.getConstantOperandAPInt(1);
4717 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
4718 unsigned InSize = N0.getOperand(0).getValueSizeInBits();
4754 EVT newVT = N0.getOperand(0).getValueType();
4761 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
4763 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
4770 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4772 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(),
4774 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
4776 EVT ExtDstTy = N0.getValueType();
4784 assert(ExtDstTy == N0.getOperand(0).getValueType() &&
4787 SDValue ZextOp = DAG.getNode(ISD::AND, dl, ExtDstTy, N0.getOperand(0),
4798 if ((N0.getOpcode() == ISD::SETCC || VT.getScalarType() != MVT::i1) &&
4799 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) &&
4800 (N0.getValueType() == MVT::i1 ||
4801 getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) &&
4803 N0, APInt::getBitsSetFrom(N0.getValueSizeInBits(), 1))) {
4806 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
4808 if (N0.getOpcode() == ISD::SETCC) {
4809 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4810 CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType());
4812 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
4813 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
4817 if ((N0.getOpcode() == ISD::XOR ||
4818 (N0.getOpcode() == ISD::AND &&
4819 N0.getOperand(0).getOpcode() == ISD::XOR &&
4820 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
4821 isOneConstant(N0.getOperand(1))) {
4824 unsigned BitWidth = N0.getValueSizeInBits();
4825 if (DAG.MaskedValueIsZero(N0,
4830 if (N0.getOpcode() == ISD::XOR) {
4831 Val = N0.getOperand(0);
4833 assert(N0.getOpcode() == ISD::AND &&
4834 N0.getOperand(0).getOpcode() == ISD::XOR);
4836 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
4837 N0.getOperand(0).getOperand(0),
4838 N0.getOperand(1));
4845 SDValue Op0 = N0;
4892 if (N0.getOpcode() == ISD::UREM && N1C->isZero() &&
4894 KnownBits XKnown = DAG.computeKnownBits(N0.getOperand(0));
4895 KnownBits YKnown = DAG.computeKnownBits(N0.getOperand(1));
4897 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
4903 N0.getOpcode() == ISD::SRA && isa<ConstantSDNode>(N0.getOperand(1)) &&
4904 N0.getConstantOperandAPInt(1) == OpVT.getScalarSizeInBits() - 1 &&
4906 return DAG.getSetCC(dl, VT, N0.getOperand(0),
4912 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
4945 return DAG.getSetCC(dl, VT, N0,
4965 return DAG.getSetCC(dl, VT, N0,
4980 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
4984 return DAG.getSetCC(dl, VT, N0,
4985 DAG.getConstant(MinVal, dl, N0.getValueType()),
4998 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
5002 return DAG.getSetCC(dl, VT, N0,
5003 DAG.getConstant(MaxVal, dl, N0.getValueType()),
5012 VT, N0, N1, Cond, DCI, dl))
5021 if ((CmpZero || CmpNegOne) && N0.hasOneUse()) {
5051 unsigned EltBits = N0.getScalarValueSizeInBits();
5063 if (IsConcat(N0, Lo, Hi))
5066 if (N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR) {
5068 if (IsConcat(N0.getOperand(0), Lo0, Hi0) &&
5069 IsConcat(N0.getOperand(1), Lo1, Hi1)) {
5070 return MergeConcat(DAG.getNode(N0.getOpcode(), dl, OpVT, Lo0, Lo1),
5071 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1));
5085 return DAG.getSetCC(dl, VT, N0,
5093 return DAG.getSetCC(dl, VT, N0,
5104 EVT ShValTy = N0.getValueType();
5111 getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) &&
5114 N0.getOpcode() == ISD::AND) {
5115 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5123 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5134 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5145 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
5146 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5152 ISD::SRL, dl, ShValTy, N0.getOperand(0),
5181 DAG.getNode(ISD::SRL, dl, ShValTy, N0,
5190 if (!isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1)) {
5199 return DAG.getSetCC(dl, VT, N0, N0, Cond);
5202 if (N0.getOpcode() == ISD::FNEG) {
5205 isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
5206 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
5207 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
5212 if (isOperationLegalOrCustom(ISD::IS_FPCLASS, N0.getValueType()) &&
5214 bool IsFabs = N0.getOpcode() == ISD::FABS;
5215 SDValue Op = IsFabs ? N0.getOperand(0) : N0;
5228 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
5243 isCondCodeLegal(NewCond, N0.getSimpleValueType()))
5244 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
5249 if (N0 == N1) {
5252 assert(!N0.getValueType().isInteger() &&
5266 isCondCodeLegal(NewCond, N0.getSimpleValueType())))
5267 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
5275 N0.getValueType().isInteger()) {
5276 if (isBitwiseNot(N0)) {
5278 return DAG.getSetCC(dl, VT, N1.getOperand(0), N0.getOperand(0), Cond);
5281 !DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(0))) {
5283 return DAG.getSetCC(dl, VT, Not, N0.getOperand(0), Cond);
5289 N0.getValueType().isInteger()) {
5290 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
5291 N0.getOpcode() == ISD::XOR) {
5293 if (N0.getOpcode() == N1.getOpcode()) {
5294 if (N0.getOperand(0) == N1.getOperand(0))
5295 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
5296 if (N0.getOperand(1) == N1.getOperand(1))
5297 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
5298 if (isCommutativeBinOp(N0.getOpcode())) {
5300 if (N0.getOperand(0) == N1.getOperand(1))
5301 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
5303 if (N0.getOperand(1) == N1.getOperand(0))
5304 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
5314 if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5316 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse())
5318 dl, VT, N0.getOperand(0),
5320 dl, N0.getValueType()),
5324 if (N0.getOpcode() == ISD::XOR && N0.getNode()->hasOneUse())
5326 dl, VT, N0.getOperand(0),
5328 dl, N0.getValueType()),
5333 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
5334 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse())
5336 dl, VT, N0.getOperand(1),
5338 dl, N0.getValueType()),
5350 if (!LegalRHSImm || N0.hasOneUse())
5351 if (SDValue V = foldSetCCWithBinOp(VT, N0, N1, Cond, dl, DCI))
5357 if (SDValue V = foldSetCCWithBinOp(VT, N1, N0, Cond, dl, DCI))
5360 if (SDValue V = foldSetCCWithAnd(VT, N0, N1, Cond, dl, DCI))
5365 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
5366 N0.hasOneUse() && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
5370 if (N0.getOpcode() == ISD::UREM) {
5371 if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
5373 } else if (N0.getOpcode() == ISD::SREM) {
5374 if (SDValue Folded = buildSREMEqFold(VT, N0, N1, Cond, DCI, dl))
5381 if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
5386 Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
5387 N0 = DAG.getNOT(dl, Temp, OpVT);
5392 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
5396 Temp = DAG.getNOT(dl, N0, OpVT);
5397 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
5404 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
5410 Temp = DAG.getNOT(dl, N0, OpVT);
5411 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
5418 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
5423 DCI.AddToWorklist(N0.getNode());
5426 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
5428 return N0;
6254 SDValue N0 = N->getOperand(0);
6259 // If N0 is negative, we need to add (Pow2 - 1) to it before shifting right.
6261 SDValue Cmp = DAG.getSetCC(DL, CCVT, N0, Zero, ISD::SETLT);
6262 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6263 SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
6351 SDValue N0 = N->getOperand(0);
6419 SDValue Q = GetMULHS(N0, MagicFactor);
6426 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
6481 SDValue N0 = N->getOperand(0);
6486 unsigned KnownLeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
6559 SDValue Q = N0;
6610 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
6635 return DAG.getSelect(dl, VT, IsOne, N0, Q);