Lines Matching defs:LL
4712 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0LL, dl, newVT), Cond);
7546 MulExpansionKind Kind, SDValue LL,
7566 // LL, LH, RL, and RH must be either all NULL or all set to a value.
7567 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
7568 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
7588 if (!LL.getNode() && !RL.getNode() &&
7590 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
7594 if (!LL.getNode())
7601 if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
7618 if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
7640 if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
7646 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
7663 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
7707 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
7719 SDValue LL, SDValue LH, SDValue RL,
7724 DAG, Kind, LL, LH, RL, RH);
7757 SDValue LL, SDValue LH) const {
7813 assert(!LL == !LH && "Expected both input halves or no input halves!");
7814 if (!LL)
7815 std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT);
7823 PartialRem = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
7827 LL = DAG.getNode(
7829 DAG.getNode(ISD::SRL, dl, HiLoVT, LL,
7843 Sum = DAG.getNode(ISD::UADDO, dl, VTList, LL, LH);
7847 Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
7848 SDValue Carry = DAG.getSetCC(dl, SetCCType, Sum, LL, ISD::SETULT);
7873 SDValue Dividend = DAG.getNode(ISD::BUILD_PAIR, dl, VT, LL, LH);
10517 const SDValue LL, const SDValue LH,
10539 EVT VT = LL.getValueType();
10544 SDValue LLL = DAG.getNode(ISD::AND, dl, VT, LL, Mask);
10552 SDValue LLH = DAG.getNode(ISD::SRL, dl, VT, LL, Shift);
10572 DAG.getNode(ISD::MUL, dl, VT, RH, LL),
10585 SDValue Args[] = {LL, LH, RL, RH};
10588 SDValue Args[] = {LH, LL, RH, RL};