Lines Matching defs:IsFSHL
2136 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
2144 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
2152 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
2153 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
2161 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
2162 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
2163 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
2164 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
7927 bool IsFSHL = Node->getOpcode() == ISD::VP_FSHL;
7938 ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt, Mask,
7940 ShY = DAG.getNode(ISD::VP_SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt, Mask,
7960 if (IsFSHL) {
7991 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
7997 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL;
8009 if (IsFSHL) {
8030 ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt);
8031 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt);
8048 if (IsFSHL) {