Lines Matching defs:HiLoVT
7545 EVT HiLoVT, SelectionDAG &DAG,
7552 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
7554 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
7556 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
7558 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
7564 unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
7570 SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
7579 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
7580 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
7589 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
7590 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
7591 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
7605 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
7630 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
7632 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
7634 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
7646 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
7647 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
7648 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
7649 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
7673 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
7686 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7693 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
7696 Hi = DAG.getNode(ISD::UADDO_CARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
7711 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7713 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7717 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
7723 N->getOperand(0), N->getOperand(1), Result, HiLoVT,
7756 EVT HiLoVT, SelectionDAG &DAG,
7776 HiLoVT.getScalarSizeInBits() == HBitWidth && "Unexpected VTs");
7785 if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) &&
7786 !isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT))
7815 std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT);
7823 PartialRem = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
7824 DAG.getConstant(Mask, dl, HiLoVT));
7828 ISD::OR, dl, HiLoVT,
7829 DAG.getNode(ISD::SRL, dl, HiLoVT, LL,
7830 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl)),
7831 DAG.getNode(ISD::SHL, dl, HiLoVT, LH,
7833 HiLoVT, dl)));
7834 LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH,
7835 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
7840 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), HiLoVT);
7841 if (isOperationLegalOrCustom(ISD::UADDO_CARRY, HiLoVT)) {
7842 SDVTList VTList = DAG.getVTList(HiLoVT, SetCCType);
7845 DAG.getConstant(0, dl, HiLoVT), Sum.getValue(1));
7847 Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
7851 if (getBooleanContents(HiLoVT) ==
7853 Carry = DAG.getZExtOrTrunc(Carry, dl, HiLoVT);
7855 Carry = DAG.getSelect(dl, HiLoVT, Carry, DAG.getConstant(1, dl, HiLoVT),
7856 DAG.getConstant(0, dl, HiLoVT));
7857 Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, Sum, Carry);
7865 // Perform a HiLoVT urem on the Sum using truncated divisor.
7867 DAG.getNode(ISD::UREM, dl, HiLoVT, Sum,
7868 DAG.getConstant(Divisor.trunc(HBitWidth), dl, HiLoVT));
7869 SDValue RemH = DAG.getConstant(0, dl, HiLoVT);
7887 std::tie(QuotL, QuotH) = DAG.SplitScalar(Quotient, dl, HiLoVT, HiLoVT);
7897 RemL = DAG.getNode(ISD::SHL, dl, HiLoVT, RemL,
7898 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
7899 RemL = DAG.getNode(ISD::ADD, dl, HiLoVT, RemL, PartialRem);
7902 Result.push_back(DAG.getConstant(0, dl, HiLoVT));